Register file write power reduction mechanism
AssigneeInternational Business Machines Corporation
InventorDavid A. Luick
Life of this patent
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Abstract
A system and method for reducing the power consumption in a floating point unit of a processor executing an iterative loop of a program by inhibiting floating point register file writes of interim values of the loop from the floating point multiply adder (FPMADD) unit. A plurality of pipeline registers is resident on the processor and holds a portion of an unrolled loop, and once the end of the loop is detected, the last value produced from the loop in the FPMADD unit is written to the floating point registers.
Claims10
A system for reducing the power consumption in a floating point unit of a processor, the processor selectively executing iterative loops of a program, each loop comprised of a sequence of instructions, the system comprising:
- a processor including a floating point unit having one or more floating point registers, and at least a floating point multiply adder (FPMADD) unit, wherein iterative calculations of each loop of the program are performed in the FPMADD unit, and the processor further having a plurality of pipeline registers for holding a portion of an unrolled sequence of the instructions of an iterative loop;
- and
- wherein writes of the floating point registers from the FPMADD unit are inhibited after the initial execution in an iterative loop of the program, and upon the detection of the last calculation of the iterative loop, the last value produced from the loop in the FPMADD unit is written to the one or more floating point registers.
A system for reducing the power consumption in a floating point unit of a processor, the processor selectively executing iterative loops of a program, the system comprising:
- a processor including a floating point unit having one or more floating point registers, and at least a floating point multiply adder (FPMADD) unit, wherein iterative calculations of each loop of the program are performed in the FPMADD unit;
- and
- a write inhibiting means for inhibiting writes of the floating point registers from the FPMADD after the initial execution in an iterative loop of the program, and upon the detection of the last calculation of the iterative loop, the write inhibiting means permitting the last value produced from the loop in the FPMADD to be written to the one or more floating point registers.
A method for reducing the power consumption in a floating point unit of a processor, the processor including a floating point unit having one or more floating point registers, and at least a floating point multiply adder (FPMADD) unit, wherein iterative calculations of each loop of the program are performed in the FPMADD unit, the processor further having a plurality of pipeline registers for holding a portion of an unrolled sequence of the instructions of an iterative loop, and the processor selectively executing iterative loops of a program where each loop is comprised of a sequence of instructions, the method comprising the steps of:
- performing a first iteration of a loop held within the pipeline registers wherein the iteration produces values at the FPMADD unit;
- inhibiting writes to the one or more floating point registers from the FPMADD unit;
- performing the last iteration of the loop held within the pipeline registers wherein the iteration produces values at the FPMADD unit;
- detecting the last iteration of the loop;
- and
- upon detecting the last iteration of the loop, writing the last value produced from the loop from the FPMADD unit to the one or more floating point registers.
Dependencies are inferred from the claim text.