Power reduction mechanism for floating point register file reads
AssigneeInternational Business Machies Corporation
InventorDavid A. Luick
Life of this patent
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Abstract
A system and method for reducing power consumed by a floating unit performing iterative calculations in a loop through selectively inhibiting floating point register file reads. One or more source register address values are compared with one or more current values generated from a first iteration of a loop, and upon determining that one ore or more values in the source registers are the same as one or more current generated values, floating point register file reads of the equal values from the one or more source registers are inhibited. The current generated values from the first iteration of the loop are preferably held in one or more pipeline registers.
Claims9
A system for reducing the floating point register file reads during an iterative loop on a processor, comprising:
- a processor including a floating point unit having a floating point register, and one or more source registers, the processor selectively executing iterative loops;
- and
- a register read monitor that compares a source register address value with a current value generated from one iteration of a loop, and upon determining that the value in the source register is the same as the current generated value, the monitor inhibiting a floating point register file read of the equal value from the one or more source registers.
A system for reducing the floating point register file reads during an iterative loop on a processor, comprising:
- a processor including a floating point unit having a floating point register, and one or more source registers, the processor selectively executing iterative loops;
- a register read monitor means for comparing a source register value with a current value generated from one iteration of a loop, and upon determining that the value in the source register is the same as the current generated value, the monitor means inhibiting a floating point register file read of the equal value from the one or more source registers.
A method for reducing the floating point register file reads during an iterative loop on a processor including a floating point unit having a floating point register, and one or more source registers, the processor selectively executing iterative loops, the method comprising the steps of:
- obtaining one or more source operands from the one or more source registers;
- performing a first calculation of an iterative loop on the obtained source operands to generate one or more current values;
- obtaining one or more source operands from the one more source registers;
- comparing the obtained one or more source operands with the current value generated from one iteration of a loop;
- and
- upon determining that the value of the one or more obtained source operands is the same as the one or more current generated values, selectively inhibiting a floating point register file read of the equal value from the one or more source registers prior to a second calculation of the iterative loop.
Dependencies are inferred from the claim text.