Data extraction/insertion method and device in digital signal processor
AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Jae Chung, Yong-Chun Kim
Life of this patent
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Abstract
A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.
Claims18
A data extraction method in a digital signal processor, wherein the digital signal processor includes a source register and a destination register, and extracting data from the source register and storing the extracted data in the destination register using a position value, the position value representing the reference position of data extraction, and an offset value, the offset value representing the size of data to be extracted, the data extraction method comprising:
- (a) storing the data of an M-th memory block in a memory having a plurality of N-bit memory blocks, into an upper portion of the source register, and storing the data of an (M+1)th memory block into a lower portion of the source register, wherein M and N are natural numbers;
- (b) extracting data of the size corresponding to the offset value, from the position corresponding to the position value in the source register, storing the extracted data in the destination register, and summing the position value and the offset value to obtain a new position value;
- (c) determining whether the new position value is greater than a predetermined modulo value, generating a flag signal in a first logic level if the new position value is smaller than the modulo value, and generating a flag signal in a second logic level if the new position value is greater than the modulo value;
- (d) repeating steps (b) and (c) using the new position value if the flag signal has a first logic level, and storing the data of the lower portion of the source register in the upper portion of the source register if the flag signal is in a second logic level;
- and
- (e) storing the data of an (M+2)th memory block of the memory in the lower portion of the source register in response to the flag signal in the second logic level, setting a next position value by the difference between the new position value and the modulo value, and going back to step (b).
A data insertion method in a digital signal processor, the digital signal processor including a source register and a destination register and inserting data from the source register into the destination register using a position value, the position value representing the reference position into which the data is to be inserted, and an offset value, the offset value representing a size of data to be inserted, the data insertion method comprising:
- (a) inserting data of the size corresponding to the offset value in the source register, into the position corresponding to the position value in the destination register to store therein, and summing the position value and the offset value to obtain a new position value;
- (b) determining whether the new position value is greater than a predetermined modulo value, and generating a flag signal in a first logic level if the new position value is smaller than the modulo value, or generating a flag signal in a second logic level if the new position value is greater than the modulo value;
- (c) repeating steps (a) and (b) using the new position value if the flag signal has a first logic level, or storing the data of the upper half of the destination register in the M-th memory block of a memory having a plurality of N-bit memory blocks if the flag signal is in a second logic level, wherein M and N are natural numbers;
- and
- (d) storing the data of the lower half of the destination register in the upper half of the destination register and setting a next position value by the difference between the new position value and the modulo value, in response to the flag signal having the second logic level, and going back to step (a).
A data extraction and insertion device, the device comprising:
- a data extraction and insertion unit for receiving a pre-position value and an offset value representing a size of data to be extracted, extracting or inserting data from a source register to a destination register in response to a first logic level of a flag signal, and storing data received from a memory in a source or destination register or storing data received from the source or destination register in the memory in response to a second logic level of the flag signal;
- a position value generation unit for summing the pre-position value and the offset value both received from external sources to obtain a position value;
- and
- a flag signal generation unit for receiving the position value, outputting the position value as the pre-position value if the position value is smaller than a predetermined modulo value, outputting the difference between the position value and the modulo value to serve as the pre-position value if the position value is greater than the modulo value, and generating a flag signal depending on the result of the comparison of the position value with the modulo value.
A DSP having a data extraction and insertion device comprising:
- a position value generation unit for summing a pre-position value and an offset value both received from external sources to obtain a position value;
- a flag signal generation unit for receiving the position value, outputting the position value as the pre-position value if the position value is smaller than a predetermined modulo value, outputting the difference between the position value and a modulo value to serve as the pre-position value if the position value is greater than the modulo value, and generating a flag signal depending on the result of the comparison of the position value with the modulo value;
- and
- means for extracting and inserting a sequence of data packets independent of byte or word size, wherein said means receives the pre-position value and the offset value, extracts or inserts data from a source register to a destination register in response to a first logic level of a flag signal, and stores data received from a memory in a source or destination register or stores data received from the source or destination register in the memory in response to a second logic level of the flag signal.
Dependencies are inferred from the claim text.