Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core

A computer system comprising:

• a switch network;
• at least one adaptive processor element comprising a first control FPGA, a system interface bus coupled to said control FPGA for coupling said processor element to said switch network, dynamic random access memory (DRAM) coupled to said control FPGA, dual-ported static random access memory (SRAM) having a first port thereof coupled to said control FPGA and a user array comprising at least one second user FPGA coupled to a second port of said dual-ported SRAM;
• at least one processor coupled to said switch network;
• and
• a shared memory resource coupled to said switch network.

A computer system comprising:

• a network;
• at least one processor coupled to said network;
• a switch network adapter port in operative association with said at least one processor;
• at least one adaptive processor element comprising a first control FPGA, a system interface bus coupled to said control FPGA for coupling said processor element to said switch network adapter port, a peripheral interface bus coupled to said control FPGA, dynamic random access memory (DRAM) coupled to said control FPGA, dual-ported static random access memory (SRAM) having a first port thereof coupled to said control FPGA and a user array comprising at least one second user FPGA coupled to a second port of said dual-ported SRAM;
• and
• at least one storage element coupled to said peripheral interface bus.

A circuit board having opposite first and second sides thereof, said circuit board comprising:

• first and second pluralities of bonding pads affixed in a generally mirror image relationship to one another on said opposite first and second sides of said circuit board respectively;
• first and second integrated circuit devices having programmable input/output pins bonded to a subset of said first and second pluralities of bonding pads respectively;
• and
• a plurality of vias formed intermediate said opposite first and second sides of said circuit board for electrically interconnecting opposing ones of said subset of said first and second pluralities of bonding pads.