Method of and system for efficiently tracking memory access by direct memory access controller
AssigneeRicoh Company, Ltd.
InventorMutsumi Namba
Life of this patent
Estimating the term…
Abstract
The debug controller makes an efficient use of memory in tracing the direct memory access by the processor and the direct memory access controller for the purpose of debugging. The direct memory access for read and write is efficiently traced by first writing a next access memory address at a currently accessing memory address.
Claims19
An input output control device connected to a memory, a processor and an input output device for controlling an interface among the memory, the processor and the input output device, the processor and the input output device sharing the memory via the interface provided by the input output control device, the input output control device comprising:
- a direct memory access controller for controlling direct memory access to the memory by the input output device;
- an arbiter connected to said direct memory access controller and the processor for arbitrating the access to the memory by the processor and said direct memory access controller;
- an memory controller connected to the memory for controlling an interface with the memory;
- and
- a debug controller connected to said arbiter and said memory controller for issuing said memory controller a memory write request for access address information for debugging in response to a direct memory access request from said direct memory access controller.
A computer system comprising:
- a memory;
- a processor;
- an input output device;
- and
- an input output control device connected to said memory, said processor and said input output device for controlling an interface among said memory, said processor and said input output device, said processor and said input output device sharing said memory via the interface provided by said input output control device, said input output control device further comprising:
- a direct memory access controller for controlling direct memory access to the memory by the input output device;
- an arbiter connected to said direct memory access controller and the processor for arbitrating the access to the memory by the processor and said direct memory access controller;
- an memory controller connected to the memory for controlling an interface with the memory;
- and
- a debug controller connected to said arbiter and said memory controller for issuing said memory controller a memory write request for access address information for debugging in response to a direct memory access request from said direct memory access controller.
A method of tracing direct memory access, an input output control device is connected to a memory, a processor and an input output device for controlling an interface among the memory, the processor and the input output device, the processor and the input output device sharing the memory via the interface provided by the input output control device, the method comprising the steps of:
- receiving at a debug controller a direct memory access request via an arbiter;
- issuing a memory controller from the debug controller a memory write request for access address information for debugging in response to the direct memory access request from a direct memory access controller;
- and
- accessing the memory based upon the memory access request.
A method of tracing direct memory access, an input output control device is connected to a memory, a processor and an input output device for controlling an interface among the memory, the processor and the input output device, the processor and the input output device sharing the memory via the interface provided by the input output control device, the method comprising the steps of:
- receiving at a debug controller a direct memory access request via an arbiter;
- issuing a memory controller from the debug controller a memory write request for access address information for debugging in response to the direct memory access request from a direct memory access controller;
- writing at least a next access address in the memory prior to performing a memory access;
- and
- accessing the memory based upon the direct memory access request.
Dependencies are inferred from the claim text.