Combined e-beam and optical exposure semiconductor lithography
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChin-Hsiang Lin
Life of this patent
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Abstract
Combined e-beam and optical exposure lithography for semiconductor fabrication is disclosed. E-beam direct writing to is employed to create critical dimension (CD) areas of a semiconductor design on a semiconductor wafer. Optical exposure lithography is employed to create non-CD areas of the semiconductor design on the semiconductor CD's of the semiconductor design can also be separated from non-CD's of the semiconductor design prior to employing e-beam direct writing and optical exposure lithography.
Claims20
A method for fabricating one or more semiconductor devices according to a semiconductor design on a semiconductor wafer comprising:
- employing electron (e-) beam direct writing to create critical dimension (CD) areas of the semiconductor design on the semiconductor wafer;
- and
- employing optical exposure lithography to create non-CD areas of the semiconductor design on the semiconductor wafer.
A method for separating critical dimensions (CD's) of a semiconductor design from non-CD's of the semiconductor design comprising:
- applying a CD rule governing which of a plurality of dimensions of the semiconductor design are the CD's to each of the plurality of dimensions of the semiconductor design to initially define the CD's to a first layer for electron (e-) beam direct writing on a semiconductor wafer;
- and
- defining the non-CD's to a second layer for optical exposure lithography on the semiconductor wafer.
A method for separating critical dimensions (CD's) of a semiconductor design from non-CD's of the semiconductor design comprising:
- defining the CD's of the semiconductor design to a first layer for electron (e-) beam direct writing on a semiconductor wafer as gate-shrink polysilicon areas of polysilicon gate layers of the semiconductor design, the semiconductor design also having OD-active layers;
- and
- defining the non-CD's of the semiconductor design to a second layer for optical exposure lithography on the semiconductor wafer as non-gate shrink polysilicon areas of the polysilicon gate layers of the semiconductor design.
Dependencies are inferred from the claim text.