Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
AssigneeInternational Business Machines Corporation
InventorsDonald W. Brouillette, Robert F. Cook, Thomas G. Ference, Wayne J. Howell, Eric G. Liniger, Ronald L. Mendelson
Life of this patent
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Abstract
A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.
Claims37
A method of processing a semiconductor structure, comprising the steps of:
- (a) providing a plurality of edges extending from a first planar surface partially through the thickness of said semiconductor structure;
- and
- (b) cutting grooves in a second planar surface opposite to said first planar surface in registry with said edges effective to dice said structure into a plurality of die units.
A method of dicing semiconductors, comprising the steps of:
- a) providing a wafer having a first major side and an opposite second major side, said wafer having a thickness dimension extending normally between said first and second major sides;
- b) partially cutting through said wafer in said thickness dimension from said second major side to provide a trench in said wafer;
- and
- c) cutting through said wafer from said first major side to intersect said trench and subdivide said wafer.
A semiconductor structure, comprising a semiconductor chip having a plurality of chamfered edges extending from one planar surface partially through the thickness of said chip.
A semiconductor structure as recited in claim 21, further comprising semiconductor devices formed in a planar surface of said chip opposite to said planar surface having said chamfered edges formed therein.
A semiconductor structure as recited in claim 22, wherein said carrier is a semiconductor chip.
A multi-chip semiconductor structure, comprising:
- a semiconductor primary chip having opposite first and second major surfaces and a first side edge oriented normal to said first and second major surfaces;
- a semiconductor secondary chip having opposite third and fourth major surfaces and a second side edge oriented normal to said third and fourth major surfaces;
- said semiconductor secondary chip being attached substantially co-planarly to said semiconductor primary chip, wherein said third major surface of said semiconductor secondary chip faces inward towards said first major surface of said semiconductor primary chip while said fourth major surface of said semiconductor secondary chip faces away from said semiconductor primary chip, and wherein said first and second side edges are laterally offset relative to each other to leave exposed a lateral edge area of said semiconductor primary chip, and wherein a beveled edge is formed in said semiconductor secondary chip extending from said fourth major surface to said second side edge of said semiconductor secondary chip without intersecting said third major surface.
A semiconductor integrated circuit package, comprising:
- a semiconductor wafer having opposite frontside and backside major surfaces and first and second side edges extending in normal directions to said frontside and backside major surfaces, wherein active devices are provided on said frontside major surface, and wherein a first beveled edge is formed in said semiconductor wafer extending from said backside major surface to said first side edge without intersecting said frontside major surface and a second beveled edge is formed in said semiconductor wafer extending from said backside major surface to said second side edge without intersecting said frontside major surface;
- and
- a plastic encapsulant covering said backside major surface and said first and second sides edges of said wafer.
A device for dicing a semiconductor wafer from one side and then the other into a plurality of die units, comprising:
- (a) a chuck to hold a wafer;
- (b) a cutting device;
- and
- (c) an alignment system for aligning said cutting device to cut from either side of the wafer given alignment marks on only one side of said wafer.
Dependencies are inferred from the claim text.