Sample clock extracting circuit and baseband signal receiving circuit

A baseband signal receiving circuit, comprising:

• a sampling circuit for sampling an input baseband signal in a given clock phase of N types of clock phases each having a frequency equivalent to N (where N is an integer greater than or equal to 2) times a symbol transmission rate of the baseband signal;
• and
• a sample clock extracting circuit having
• a number-of-change point memory for storing a number-of-change-point information set every N types of clock phases each having a frequency equivalent to N (where N is an integer greater than or equal to 2) times a symbol transmission rate of an input baseband signal;
• a number-of-change point updating circuit for updating the number-of-change point information stored in the number-of-change point memory about a clock phase related to timing thereof when a rising change point or a falling change point occurs in the baseband signal;
• and
• an output clock phase determining circuit for determining a clock phase directly or indirectly indicative of a sample clock phase for the baseband signal based on the number-of-change-point information stored in the number-of-change point memory.

A word detecting circuit comprising:

• a high-speed sampling data memory for sequentially storing data obtained by sampling the baseband signal at a clock frequency equivalent to N (where N is an integer greater than or equal to 2) times a symbol transmission rate of the baseband signal;
• a data taking-out circuit for taking out data from the data stored in the high-speed sampling data memory means by a number equal to the number of bits for the predetermined word and such that data prior to and subsequent to each other have a time difference developed therebetween, corresponding to N clocks of the clock frequency;
• a coincidence/non-coincidence comparing circuit for detecting coincidence and non-coincidence between respective bits for the taken-out data and respective bits for the predetermined word;
• and
• a word detecting circuit for determining whether the predetermined word has been detected, and a detection phase at the detection of the predetermined word from the N types of clock phases, based on the result of comparison by the coincidence/non-coincidence comparing circuit.

A baseband signal receiving circuit comprising:

• a sampling circuit for sampling an input baseband signal in a given clock phase of N types of clock phases each having a frequency equivalent to N (where N is an integer greater than or equal to 2) times a symbol transmission rate of the baseband signal;
• and
• a word detecting circuit including
• a high-speed sampling data memory for sequentially storing data obtained by sampling the baseband signal at a clock frequency equivalent to N (where N is an integer greater than or equal to 2) times a symbol transmission rate of the baseband signal;
• a data taking-out circuit for taking out data from the data stored in the high-speed sampling data memory means by a number equal to the number of bits for the predetermined word and such that data prior to and subsequent to each other have a time difference developed therebetween, corresponding to N clocks of the clock frequency;
• a coincidence/non-coincidence comparing circuit for detecting coincidence and non-coincidence between respective bits for the taken-out data and respective bits for the predetermined word;
• and
• a word detecting circuit for determining whether the predetermined word has been detected, and a detection phase at the detection of the predetermined word from the N types of clock phases, based on the result of comparison by the coincidence/non-coincidence comparing circuit.