Synchronous semiconductor device having constant data output time regardless of bit organization, and method of adjusting data output time

A synchronous semiconductor device comprising:

• a delay-locked loop circuit to receive an external clock and generate a data output clock;
• and
• a data output circuit to output data read from a memory cell to the outside in response to the data output clock,
• wherein the delay-locked loop circuit comprises:
• a phase comparator to compare the phase of external clock with the phase of a feedback signal and generate a detection signal corresponding to a difference between their phases;
• a delay controller to receive the detection signal and generating a delay control signal;
• a delayer to delay the external clock for a predetermined time in response to the delay control signal and generating the data output clock;
• and
• a compensation delay controller to delay the data output clock in response to the bit organization information and generate the feedback signal.

A method of regularly adjusting data output time of a synchronous semiconductor device regardless of bit organization, the method comprising:

• receiving an external clock and generating an internal clock;
• adjusting the phase of the internal clock according to the bit organization and generating a data output clock;
• and
• outputting data read from a memory cell to the outside in response to the data output clock.

A method of regularly adjusting a synchronous semiconductor device regardless of bit organization, the method comprising:

• comparing the phase of an external clock with the phase of a feedback signal and generating a detection signal corresponding to a difference between their phases;
• generating a delay control signal in response to the detection signal;
• delaying the external clock for a predetermined time in response to the delay control signal and generating a data output clock;
• adjusting the phase of the data output clock according to the bit organization and generating the feedback signal;
• and
• outputting data read from a memory cell to the outside in response to the data output clock.