Decoder arrangement of a memory cell array
AssigneeMacronix International Co., Ltd.
InventorsTom D. Yiu, Ful L. Ni
Life of this patent
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Abstract
A hybrid memory cell array including a preferable arrangement of a row decoder is proposed, and in the same manner of addressing a memory cell in the memory array a high access speed of the memory cell and high integration layout of a memory chip can be achieved. A hybrid memory cell includes a plurality of memory cells that each includes an electronic circuit to store binary logic values, a plurality of word lines, a plurality of bit lines, a row decoder arranged in the memory cell array to enable the plurality of word lines and select a memory cell on a same word line, and a column decoder arranged outside the memory cell array to enable the plurality of bit lines and select a memory cell on a same bit line.
Claims8
A hybrid memory array including:
- a first sub-array that includes a first number of columns of memory cells;
- a second sub-array that includes a second number of columns of memory cells, wherein said second number is larger than said first number;
- and
- a row decoder connecting to a first set of word lines for accessing said first sub-array and a second set of word lines for accessing said second sub-array, wherein the length of said first set of word lines is shorter than the length of said second set of word lines.
A memory array including:
- a first sub-array that includes a plurality of memory cells arranged in a first number of columns and a second number of rows;
- a second sub-array that includes a plurality of memory cells arranged in a third number of columns and a forth number of rows, wherein said third number is larger than said first number;
- a column decoder connecting to a plurality of bit lines, wherein each of said bit lines accesses to each of said first number of columns and said third number of columns respectively;
- and
- a row decoder connecting to a first set of word lines for accessing said second number of rows of said first sub-array and a second set of word lines for accessing said forth number of rows of said second sub-array, wherein the length of said first set of word lines is shorter than the length of said second set of word lines.
A method of using a hybrid memory array, wherein said hybrid memory array includes a first sub-array of a first number of columns of memory cells, a second sub-array of a second number of columns of memory cells, a row decoder deposed between and said first and second sub-arrays, and a column decoder, wherein said first number is less than said second number, said method comprising:
- using said first sub-array for a first application requiring a access speed to memory cells;
- and
- using said second sub-array for a second application requiring a larger memory cell density.
Dependencies are inferred from the claim text.