A method of erasing a programmed electrically erasable charge trap nonvolatile memory cell that includes a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein, the transistor having an initial threshold voltage and a program threshold voltage that is higher than the initial threshold voltage, the erasing method comprising:
- applying an erase voltage to the gate for a time interval that is sufficient to lower a threshold voltage of the transistor from the program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage.