Intermesh memory device
AssigneeHewlett-Packard Development Company, L.P.
InventorsAndrew Koll, Peter Fricke, Andrew L. Van Brocklin
Life of this patent
Estimating the term…
Abstract
An intermesh memory device includes memory components that each have a determinable resistance value and electronic switches that each control current through one or more of the memory components such that a potential is applied to the memory components. A first electronic switch of the intermesh memory device is electrically coupled to an input of a memory component and a second electronic switch is electrically coupled to an output of the memory component. The first electronic switch and the second electronic switch are configured together to apply a potential to the memory component.
Claims60
An intermesh memory device, comprising:
- memory components each configured to have a determinable resistance value, the memory components forming a memory array with a first set of the memory components substantially perpendicular to a second set of the memory components;
- electronic switches each configured to control current through one or more of the memory components such that a potential is applied to the one or more memory components;
- wherein a first electronic switch is electrically coupled to drive an input of a memory component and a second electronic switch is electrically coupled to sense an output of the memory component, the first electronic switch and the second electronic switch configured together to apply a potential to the memory component.
An electrical structure, comprising:
- electronic switches fabricated in a semiconductive material on a semiconductor substrate;
- electrically resistive components fabricated in a device region offset from the semiconductive material, the electrically resistive components configured to form an intermesh array of memory cells formed with a first set of the electrically resistive components intersected by a second set of the electrically resistive components;
- electrically conductive vias configured to electrically couple one or more of the electronic switches to one or more of the electrically resistive components.
A method, comprising:
- forming electronic switches on a semiconductor substrate;
- forming electrically conductive vias;
- forming memory components in an intermesh array, an individual memory component being electrically coupled to a first electronic switch with a first electrically conductive via and the individual memory component being electrically coupled to a second electronic switch with a second electrically conductive via.
An electronic device, comprising:
- means for applying a drive voltage with a drive pillar coupled to drive an input of a first memory component in an intermesh memory device;
- means for applying a sense voltage with a sense pillar coupled to sense an output of the first memory component;
- and
- means for sensing a resistance value of the first memory component, the resistance value being determinable when the drive pillar and the sense pillar are enabled.
An electronic device, comprising:
- means for enabling a first electronic switch coupled to apply a drive voltage to an input of a row memory component in an intermesh memory device;
- means for enabling a second electronic switch coupled to apply a sense voltage to an output of the row memory component;
- and
- means for sensing a resistance value of the row memory component, the resistance value being determinable when the first electronic switch and the second electronic switch are enabled.
A method, comprising:
- applying a first voltage to an input of a first memory component in an intermesh memory device, the first voltage being applied with a drive pillar coupled to the input of the first memory component;
- applying a second voltage to an output of the first memory component, the second voltage being applied with a sense pillar coupled to the output of the first memory component;
- and
- sensing a resistance value of the first memory component, the resistance value being determinable when the drive pillar and the sense pillar apply a potential to the first memory component.
Dependencies are inferred from the claim text.