US 2003/0210247 A1 · Power management for an integrated graphics device

Abstract

In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Claims29

Dependent claims

A graphics memory controller hub comprising:

a graphics core;
and
a circuit to alter a frequency of a render clock signal supplied to the graphics core, the circuit to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Dependencies are inferred from the claim text.

Facts

Application

10/143,406Filed 9 May 2002

Published

13 Nov 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 1/3228
Monitoring of events, devices or parameters that trigger a change in power modality: monitoring task completion, e.g. by use of idle timers, stop…
G06F 1/3215
Monitoring of events, devices or parameters that trigger a change in power modality: monitoring of peripheral devices
G06F 1/324
Power saving characterised by the action undertaken: by lowering clock frequency
G06F 1/325
Power saving characterised by the action undertaken: power saving in peripheral device

Power management for an integrated graphics device

Life of this patent

Power management for an integrated graphics device

Life of this patent

Abstract

Claims29