Electric circuit, latch circuit, display apparatus and electronic equipment

An electric circuit, comprising:

• a first N-type transistor;
• a P-type transistor;
• and
• a second N-type transistor,
• wherein the first N-type transistor and the P-type transistor are connected in series,
• wherein a gate electrode of the first N-type transistor is connected to a gate electrode of the P-type transistor,
• wherein a drain electrode of the first N-type transistor and a drain electrode of the P-type transistor are connected to a gate electrode of the second N-type transistor,
• wherein a source electrode of the first N-type transistor is electrically connected to a power supply, and
• wherein a signal is input to a source electrode of the P-type transistor.

A latch circuit comprising:

• a first N-type transistor and a first P-type transistor connected in series;
• a first compensating circuit for selecting an input of a data signal or an input of a first power supply potential based on an input latch signal and for outputting the selected input to a gate electrode of the first P-type transistor;
• a second compensating circuit for selecting an input of a data signal or an input of a second power supply potential based on an input inverse latch signal and for outputting the selected input to a gate electrode of the first N-type transistor,
• wherein the data signal is input from a same signal line, and
• wherein the output of the latch circuit is extracted from a connecting portion between the first N-type transistor and the first P-type transistor connecting portion.

A latch circuit comprising:

• a circuit having a first P-type transistor and a first N-type transistor, wherein a source electrode of the first P-type transistor is connected to a first power supply and a source electrode of the first N-type transistor is connected to a second power supply;
• a first compensating circuit having a second N-type transistor and a second P-type transistor, wherein gate electrodes of the second N-type transistor and second P-type transistor are connected to each other and the second N-type transistor and the second P-type transistor are connected in series;
• a second compensating circuit having a third N-type transistor and a third P-type transistor, wherein gate electrodes of the third N-type transistor and third P-type transistor are connected to each other and the third N-type transistor and third P-type transistor are connected in series;
• wherein source electrodes of the second N-type transistor and third P-type transistor are connected to a same data line,
• wherein a source electrode of the second P-type transistor is connected to the first power supply,
• wherein a source electrode of the third N-type transistor is connected to the second power supply,
• wherein drain electrodes of the second N-type transistor and second P-type transistor are connected to a gate electrode of the first P-type transistor,
• wherein drain electrodes of the third N-type transistor and third P-type transistor are connected to a gate electrode of the first N-type transistor, and
• wherein an output is extracted from a drain electrode of the first N-type transistor or first P-type transistor.