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US 2003/0209786 A1Published application
High speed IC package configuration
AssigneeMicron Technology, Inc.
InventorsDavid J. Corisis, Brent Keeth
Life of this patent
Estimating the term…
Abstract
Devices and methods for reducing lead inductance in integrated circuit (IC) packages. More specifically to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated circuit package assembly comprises a substrate, semiconductor device, insulating covering or coating, if desired, a semiconductor device retainer, lead frame, and wire bond interconnections.
Claims20
A semiconductor package assembly comprising:
- a substrate having a first side and a second side thereof;
- a semiconductor device located on the substrate, the semiconductor device having an active surface and a plurality of bond pads thereon;
- an adhesive coated insulation material covering a portion of the active surface of the semiconductor device;
- a semiconductor device retainer retaining the semiconductor device in position on the substrate having a portion engaging a portion of the first side of the substrate, a portion engaging a portion of the second side of the substrate, and a portion engaging a portion of the active surface of the semiconductor device;
- a lead frame having a plurality of leads thereon;
- and
- at least one electrical interconnection between at least one lead of the lead frame and the at least one bond pad of the semiconductor device.
4 more elements
An assembly comprising:
- a substrate having a two sides;
- a semiconductor die located on one of the two sides of the substrate, the semiconductor die having an active surface and a plurality of bond pads located thereon;
- insulation material covering a portion of the active surface of the semiconductor die;
- a semiconductor retainer device retaining the semiconductor die on the substrate, the semiconductor device retainer engaging a portion of the active surface of the semiconductor die and a portion of the second side of the substrate;
- a lead frame having a plurality of leads thereon;
- and
- a plurality of electrical interconnections between the plurality of leads of the lead frame and the plurality of bond pads of the semiconductor die.
4 more elements
Dependencies are inferred from the claim text.