Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure

A method of forming an array of two-bit non-volatile memory cells comprising the steps of:

• forming a first sequence of parallel isolated active area regions in a substrate,
• forming on top of and substantially perpendicular to said first sequence of parallel isolated active area regions a first sequence of interspaced cell stacks formed in a first stack of layers,
• depositing uniformly over said substrate a second stack of layers thereby substantially filling the spacing between said first sequence of interspaced gate stacks;
• and
• planarizing said second stack of layers thereby forming a second sequence of cell stacks in between and abutted by said first sequence of interspaced cell stacks.

A method for programming, reading and erasing a bit in a two-bit memory cell stack, in an array of two-bit non-volatile memory cells,

• said array comprising a first sequence of parallel isolated active area regions formed in a substrat, a second sequence of planar adjoining cell stacks, being positioned above and substantially perpendicular to said first sequence of parallel isolated active area regions, junctions formed self-aligned to and at opposite sides of said second sequence of planar adjoining cell stacks, said planar adjoining cell stacks being isolated from each other and comprising a conductive gate and a charge-storing dielectric layer, sandwiched between two dielectric layers, and comprising two regions, each region capable of storing 1 bit,
• said method comprising the steps of:
• selecting a memory cell stack;
• programming in a forward direction a bit in one of said two regions of said memory cell stack, the step of programming comprising:
• grounding one junction, positioned at the same side as said one of said two regions and applying a high potential to a junction, positioned at the opposite side of said one of said two regions;
• applying a high voltage to all cell stacks except to the cell stack neighbouring said one of said two regions to invert the active area regions underneath said biased cell stacks;
• and,
• biasing said neighbouring cell stack at a voltage slightly above the threshold voltage of said neighbouring cell stack to thereby inject electrical charge of a first type into said one of said two regions such that the threshold voltage of said selected cell stack is at least at predetermined level when said memory cell stack is read in the same direction from which it was programmed;
• reading said programmed bit in forward direction, the step of reading comprising:
• grounding said junction, positioned at the same side as said one of said two regions and applying a low potential to said junction, positioned at the opposite side of said one of said two regions;
• applying a high voltage on all cell stacks except to said selected memory cell stack to invert the active area regions underneath said biased cell stacks;
• and,
• sensing to what extent the threshold voltage of said selected memory cell is changed by said injected electrical charge.