System-on-a-chip having an on-chip processor and an on-chip dynamic random access memory (DRAM)
AssigneeSun Microsystems, Inc.
InventorsLawrence Butcher, Duane Northcutt, Marc Schneider, Gerard Wall, James Hanko, Alan Ruberg, Satyanarayana Simha, Michael E. Duboce, Arvind Srinivasan
Life of this patent
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Abstract
A system-on-a-chip device is provided, the system-on-a-chip device comprising an on-chip processor and an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor. The system-on-a-chip device also comprises at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM).
Claims30
A system-on-a-chip device comprising:
- an on-chip processor;
- an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor;
- and
- at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM).
A system-on-a-chip device comprising:
- an on-chip processor;
- an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor;
- an on-chip peripheral component interconnect (PCI) input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM);
- an on-chip arbiter capable of communicating with the on-chip peripheral component interconnect (PCI) input/output (I/O) bus;
- an on-chip expansion bus (E-Bus) input/output (I/O) bus;
- an on-chip expansion bus (E-Bus) controller capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus;
- an on-chip Ethernet controller;
- an on-chip USB Host controller;
- an on-chip universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus;
- an on-chip Smart Card Interface (SCI) universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus;
- an on-chip I2C universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus;
- an on-chip GPIO capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus;
- an on-chip joint test access group (JTAG) device;
- an on-chip AC97 interface capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus;
- and
- a private flash bus capable of latching configuration options at power-up.
A system-on-a-chip method comprising:
- providing an on-chip processor for a system-on-a-chip device;
- providing an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor;
- and
- providing at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM).
Dependencies are inferred from the claim text.