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US 2003/0207490 A1Published application
Wafer level underfill and interconnect process
AssigneeInternational Rectifier Corporation
InventorMartin Standing
Life of this patent
Estimating the term…
Abstract
A chip scale package and a method for its manufacture which include providing sticky interconnects on a surface of a semiconductor die, the interconnects being surrounded by a layer of thermal epoxy.
Claims8
A semiconductor device, comprising:
- a semiconductor die having a major surface;
- an electrical contact on said major surface of said semiconductor die;
- an interconnect on said electrical contact, said interconnect being composed of a sticky epoxy containing conductive particles;
- and
- a layer of thermal epoxy disposed on said major surface and surrounding said interconnect.
2 more elements
Dependencies are inferred from the claim text.