Devices and methods for integrated circuit manufacturing
AssigneeHewlett-Packard Development Company, L.P.
InventorsSimon Dodd, Frank Randolph Bryant, Paul I. Mikulan
Life of this patent
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Abstract
Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.
Claims28
An integrated circuit, comprising a shielding element.
A fluid ejection device, comprising an integrated circuit including a shielding element.
A print head, comprising a multi-layer integrated circuit, further comprising means for electrically isolating a sensitive section of a said circuit to prevent damaging side effects of a manufacturing process.
A process of making a multi-layered integrated circuit, comprising the steps of:
- forming, at the surface of a semiconductor die at least an insulating layer;
- etching at least said insulating layer thereby forming a surface with both semiconductor areas and insulating areas;
- doping said surface, such that said surface is formed from insulating areas and doped semiconductor areas;
- wherein said surface comprises a doped semiconductor area separated from a second doped semiconductor area by an unbroken insulator area disposed above the semiconductor die.
A process of manufacturing a multi-layered integrated circuit, comprising:
- forming one or more conducting layers;
- forming at least one shielding element isolating at least part of said one or more conducting layers;
- further processing said one or more conducting layers.
An ink jet print cartridge, comprising:
- a print head, further comprising a multilayer integrated circuit comprising a shielding element and a drill slot through at least one doped semiconductor layer;
- wherein the one doped semiconductor layer is at least substantially divided by the shielding element into a first section enclosing the drill slot and a second section.
A slot fed print head useful for ink jet printers, comprising:
- a multi-layer integrated circuit, the circuit further comprising at least a Silicon die and a cavitation layer;
- a drill slot disposed through the Silicon die;
- a doped Silicon region surrounding the drill slot at the surface of the Silicon die;
- a gate oxide enclosure substantially enclosing the doped Silicon region surrounding the drill slot and disposed directly above low conductance Silicon die;
- and
- a Polycrystalline Silicon layer disposed directly above the gate oxide enclosure, the Polycrystalline Silicon layer comprising a dissipating element connecting the Polycrystalline Silicon layer to ground.
A method of inhibiting delamination of a cavitation layer in a multi-layered integrated circuit comprising the steps of:
- forming a conductive layer;
- electrically isolating a first portion of the conductive layer from a second portion thereof with a shielding element;
- and
- depositing the cavitation layer over portions of the first portion and the second portion, and over the shielding element.
Dependencies are inferred from the claim text.