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US 2003/0207207 A1Published application
Method of fabricating a semiconductor multilevel interconnect structure
AssigneeMicron Technology, Inc.
InventorWeimin Li
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AssigneeMicron Technology, Inc.
InventorWeimin Li
Estimating the term…
A method of fabricating a semiconductor multilevel interconnect structure employs a dual hardmask technique in a dual damascene process. The method includes using amorphous carbon as a first hardmask layer capable of being etched by a second etch process, and a second hardmask layer capable of being etched by a first etch process, as a dual hardmask. By virtue of the selective etch chemistry employed with the dual hardmask, the method affords flexibility unattainable with conventional processes. The via is never in contact with the photoresist, thus eliminating residual photoresist at the trench/via edge and the potential “poisoning” of the intermetal dielectric layer. Since trench/via imaging is completed before further etching, any patterning misalignments can be easily reworked. Because the amorphous carbon layer and the second hardmask layer are used as the dual hardmask, the photoresist can be made thinner and thus optimized for the best imaging performance.
A method of fabricating a semiconductor multilevel interconnect structure, said method comprising:
A method of fabricating a semiconductor multilevel interconnect structure, said method comprising:
A method of forming an integrated circuit interconnect comprising:
A method of forming an integrated circuit interconnect comprising:
A method of forming an opening for an interconnect comprising:
A method of forming an opening for an interconnect comprising:
A structure for use in fabricating a dual damascene opening, said structure comprising:
A structure for use in fabricating a dual damascene opening, said structure comprising:
Dependencies are inferred from the claim text.