Semiconductor device array having dense memory cell array and hierarchical bit line scheme

A high-density semiconductor memory device, comprising:

• a plurality of lower-order conductive segments arranged into lower-order connected groups, each lower-order connected group including
• a first lower-order conductive segment associated with a first sense amplifier circuit,
• a second lower-order conductive segment associated with the first sense amplifier circuit, the second lower-order conductive segment being situated adjacent to the first lower-order conductive segment in a first direction,
• a third lower-order conductive segment associated with a second sense amplifier circuit, the third lower-order conductive segment being situated adjacent to the first lower-order conductive segment in a second direction that is generally perpendicular to the first direction,
• a fourth lower-order conductive segment associated with the second sense amplifier circuit, the fourth lower-order conductive segment being situated adjacent to the second lower-order conductive segment in the second direction,
• a plurality of higher-order conductive segments coupled to sense amplifiers in pairs, the higher-order conductive segments including
• a first folded pair that includes a first higher-order conductive segment and a second higher-order conductive segment, and
• a second folded pair that includes a third higher-order conductive segment and a fourth higher-order conductive segment;
• a reconnector circuit associated with each lower-order connected group, each reconnector circuit having a reconnect configuration and a switch configuration, the switch configuration
• coupling the first higher-order conductive segment to the first lower-order conductive segment,
• coupling the second higher-order conductive segment to the second lower-order conductive segment,
• coupling the third higher-order conductive segment to the third lower-order conductive segment, and
• coupling the fourth higher-order conductive segment to the fourth lower-order conductive segment, and
• the reconnect configuration isolating the higher-order conductive segments from the lower order conductive segments.

A semiconductor memory device formed in a semiconductor substrate, the memory device comprising:

• a plurality of folded bit line segment pairs;
• a plurality of open bit line segments arranged into open bit line segment pairs;
• a reconnector circuit coupled between adjacent folded bit line segment pairs and two adjacent open bit line segment pairs, the reconnector circuit having
• reconnect devices that couple the folded bit line segment pairs to one another, and
• switching devices that couple each folded bit line segment pair to one of the open bit line segment pairs;
• and
• a plurality of memory cells coupled to the open bit line segments.