US 2003/0206451 A1Published application

Monvolatile memory, semiconductor device, and method of programming to nonvolatile memory

AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.

InventorsToshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri

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Abstract

Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “1” (or logic “1) is successively performed.

Claims28

Dependent claims

A nonvolatile memory comprising:

a memory array having a plurality of word lines, a plurality of bit lines, and a plurality of nonvolatile memory cells, in which control terminals of nonvolatile memory cells in the same row are connected to a common word line, and data input/output terminals of the nonvolatile memory cells in the same column are connected to a common bit line;
a data register for holding write data of said plurality of nonvolatile memory cells;
and
a write control circuit for applying a write voltage to said bit line in accordance with write data held in the data register,
said nonvolatile memory being constructed to store data by changing a threshold voltage of said nonvolatile memory cell by applying the write voltage to said bit line,
wherein when a bit corresponding to write data held in said data register has logic “1” (or logic “0”), said write control circuit skips the bit and sequentially applies said write voltage to bit lines corresponding to the bit having the logic “0” (or logic “1”).

3 more elements

A method of writing data to a nonvolatile memory comprising:

a memory array having a plurality of word lines, a plurality of bit lines, and a plurality of nonvolatile memory cells, in which control terminals of nonvolatile memory cells in the same row are connected to a common word line, and data input/output terminals of the nonvolatile memory cells in the same column are connected to a common bit line;
and a data register for holding write data of said plurality of nonvolatile memory cells, the method for storing data by changing a threshold voltage of said nonvolatile memory cell by applying a write voltage to said bit line,
wherein when a bit of write data held in said data register has logic “1” (or logic “0”), the bit is skipped and said write voltage is sequentially applied to bit lines corresponding to the bit “0” (or a logic “1”).

Dependencies are inferred from the claim text.

Facts

Application: 10/419,228Filed 21 Apr 2003
Priority: JP 2000-3026962 Oct 2000
Published: 6 Nov 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 16/3459
Arrangements for verifying correct programming or for detecting overprogrammed cells: circuits or methods to verify correct programming of…
G11C 16/12
Programming or data input circuits: programming voltage switching circuits
G11C 2216/14
Reading and writing aspects of erasable programmable read-only memories: circuits or methods to write a page or sector of information…
G11C
Static stores

Family

Application09/964,394Continuation · filed 28 Sep 2001
Application10/419,228Continuation · filed 21 Apr 2003
US 2002/0041527 A1Published application
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US 2003/0206451 A1This patent

From the US filing history. Foreign family members aren’t listed.