Integrated chip package structure using ceramic substrate and method of manufacturing the same

A chip package structure comprising:

• a ceramic substrate;
• a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface, whereas the backside of each die is adhered to the ceramic substrate;
• and
• a thin-film circuit layer located on top of the ceramic substrate and the die and has an external circuitry, wherein the external circuitry is electrically connected to the metal pads of the die and extends to a region outside the active surface of the die, the external circuitry has a plurality of bonding pads located on a surface layer of the thin-film circuit layer and each bonding pad is electrically connected to the corresponding metal pad of the die.

A chip packaging method comprising:

• providing a ceramic substrate with a surface;
• providing a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface, whereas the backside of each die is adhered to the surface of the ceramic substrate;
• allocating a first dielectric layer on top of the surface of the ceramic substrate and the active surface of the dies;
• and
• allocating a first patterned wiring layer on top of the first dielectric layer, wherein the first patterned wiring layer is electrically connected to the metal pads of the dies through the first dielectric layer, extends to a region outside of an area above the active surfaces of the dies, and has a plurality of first bonding pads.

A chip packaging method comprising:

• providing an insulating substrate with a first surface;
• providing a plurality of dies, wherein each die has an active surface and a backside that is opposite to the active surface and a plurality of metal pads located on the active surface, whereas the active surface of each die is adhered to the first surface of the insulating substrate;
• allocating a filling layer on top of the first surface of the insulating substrate and surrounding the dies;
• planarizing and thinning of the filling layer and the dies;
• providing a ceramic substrate with a second surface and adhering the second surface of the ceramic substrate to the filling layer and the dies;
• and
• allocating a first patterned wiring layer on top of the insulating substrate, wherein the first patterned wiring layer is electrically connected to the metal pads of the dies through the insulating substrate, extends to a region outside the active surfaces of the dies, and has a plurality of first bonding pads.

A chip packaging method comprising:

• providing a substrate with a first surface;
• providing a plurality of dies, wherein each die has an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface, whereas the active surface of each die is adhered to the first surface of the substrate;
• allocating a first filling layer on top of the first surface of the substrate and surrounding the dies;
• planarizing and thinning of the first filling layer and the dies;
• providing a ceramic substrate with a second surface and adhering the second surface of the ceramic substrate to the first filling layer and the dies;
• removing the first filling layer and the substrate;
• allocating a first dielectric layer on the second surface of the ceramic substrate and the active surface of the dies;
• and
• allocating a first patterned wiring layer on top of the first dielectric layer, wherein the first patterned wiring layer is electrically connected to the metal pads of the dies through the first dielectric layer, extends to a region outside the active surfaces of the dies, and has a plurality of first bonding pads.

A chip package structure comprising:

• a ceramic substrate;
• a die module comprising an active surface, a backside that is opposite to the active surface, and a plurality of metal pads located on the active surface, whereas the backside of the die module is adhered to the ceramic substrate;
• a filling layer located on top of the ceramic substrate and surrounding a peripheral of the die module, a top surface of the filling layer is planar to the active surface of the die module;
• a thin ceramic layer located on top of the filling layer and the die module;
• and
• a thin-film circuit layer located on top of the thin ceramic layer and the die module and has an external circuitry, wherein the external circuitry is electrically connected to the metal pads of the die module and extends to a region outside the active surface of the die module, the external circuitry has a plurality of bonding pads located on a surface layer of the thin-film circuit layer and each bonding pad is electrically connected to a corresponding metal pad of the die module.