Reduction of parasitic bipolar leakage current in silicon on insulator devices
AssigneeInternational Business Machines Corporation
InventorsTodd Alan Christensen, David Michael Friend, Nghia Van Phan, John Edward Sheets II
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Abstract
A method and apparatus for reducing parasitic bipolar transistor leakage current in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS). A capacitor is operatively coupled between the base and emitter terminals of the parasitic bipolar transistor. The capacitor effectively reduces the base to emitter voltage of the parasitic transistor thereby reducing leakage current generated at the collector terminal.
Claims17
A method for reducing parasitic bipolar transistor leakage current in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device, comprising:
- providing a parasitic bipolar transistor comprising a base terminal, an emitter terminal coupled to a source terminal of the SOI MOS device, and a collector terminal coupled to a drain terminal of the SOI MOS device;
- and
- coupling a capacitor in parallel to the base terminal and emitter terminal of the parasitic bipolar transistor, wherein the capacitor reduces the base to emitter voltage of the parasitic bipolar transistor.
A circuit for reducing parasitic bipolar transistor leakage current in a Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (FET), comprising:
- a capacitor coupled in parallel with a base node and an emitter node of the parasitic bipolar transistor, wherein the capacitor is configured to reduce leakage current generated by the parasitic bipolar transistor.
A circuit, comprising:
- a silicon-on-insulator (SOI) metal oxide semiconductor (MOS) field effect transistor (FET) comprising a gate, source and drain terminal;
- a parasitic bipolar transistor comprising an emitter terminal coupled to the source terminal of the FET, a collector terminal coupled to the drain terminal of the FET and a base terminal;
- and
- a capacitor comprising a first terminal coupled to the emitter of the parasitic transistor and a second terminal coupled to the base of the parasitic transistor.
Dependencies are inferred from the claim text.