Semiconductor memory device
AssigneeHitachi, Ltd.
InventorsShinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
Life of this patent
Estimating the term…
Loading patent…
AssigneeHitachi, Ltd.
InventorsShinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
Estimating the term…
A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
In a semiconductor memory device having a switching transistor and a charge storage capacitor as a minimal unit, the improvement comprising an active region in which a channel region and source and drain regions of said switching transistor are formed and the major portion of which is so arranged as to be parallel to neither the major portions of word lines constituting said switching transistor nor the major portions of bit lines for writing and reading data, said active region being composed of a region which is inclined with respect to said word lines and a region which is at a right angle with respect to said word lines, and being also composed of a region which is inclined with respect to said bit lines and a region which is parallel with said bit lines.
In a semiconductor memory device having a switching transistor and a charge storage capacitor as a minimal unit, the improvement comprising:
A process for fabricating a semiconductor memory device having a switching transistor and a charge storage capacitor as a minimal unit, said process comprising the steps of:
In a semiconductor device of a one-transistor and one-capacitor type having a charge storage electrode which extends onto a word liner or a bit line, the improvement comprising the periphery of said charge storage electrode which is formed into a thin wall such that the inner wall surface and outer wall surface of said thin wall constitute said charge storage electrode.
A process for fabricating a semiconductor device comprising the steps of:
Dependencies are inferred from the claim text.