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US 2003/0204802 A1Published application
Multiple scan chains with pin sharing
AssigneeSamsung Electronics Co., Ltd.
InventorGyoochan Sim
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AssigneeSamsung Electronics Co., Ltd.
InventorGyoochan Sim
Estimating the term…
A scan based design architecture reduces pin count, test time and power consumption, and also allows the use of existing verified scan vectors by driving multiple scan chains from one scan input and utilizing multiple scan clocks. The scan vectors for multiple scan chains are sequentially applied to the scan input so as to broadcast the vectors to multiple scan chains, but only the bits for one scan chain are selectively clocked into that chain by a corresponding one of the multiple scan clocks. An output multiplexer can also be used to reduce the total number of test pins. The pin count can be further reduced by using a scan clock generator to generate the multiple scan clocks from a single scan clock input, and by using a select signal generator to generate select signals that control an output multiplexer.
A circuit comprising a plurality of scan chains having a plurality of scan inputs coupled to an input terminal, and a plurality of scan clock inputs coupled to receive a plurality of scan clock signals.
A circuit comprising a plurality of scan chains having a plurality of scan outputs coupled to an output terminal through a multiplexer.
A method for testing a circuit comprising a plurality of scan chains having a plurality of scan inputs and a plurality of scan outputs, the method comprising:
A method for testing a circuit comprising a plurality of scan chains having a plurality of scan inputs and a plurality of scan outputs, the method comprising shifting out data from the plurality of scan outputs through an output terminal.
A method for loading scan vectors into a circuit comprising a plurality of scan chains having a plurality of scan inputs and a plurality of scan outputs, the method comprising:
Dependencies are inferred from the claim text.