Apparatus and method for determining effect of on-chip noise on signal propagation

An apparatus for dynamically testing an integrated circuit, said integrated circuit having a core logic area with a plurality of components therein, the apparatus comprising:

• a first test circuit having a first plurality of elements connected by a first plurality of traces, said first plurality of elements and said first plurality of traces routed to mimic a data path within said integrated circuit;
• a second test circuit having a second plurality of elements connected by a second plurality of traces, said second plurality of traces being routed within said core logic area;
• a third test circuit having a third plurality of elements connected by a third plurality of traces, said third plurality of elements being randomly located within said core logic area;
• and
• a fourth test circuit having a fourth plurality of elements connected by a fourth plurality of traces, said fourth plurality of elements and said fourth plurality of traces routed to mimic a data path within said integrated circuit.

An integrated circuit, comprising:

• a core logic area having a plurality of components therein;
• a first test circuit constructed to mimic a data path within said core logic area;
• a second test circuit constructed with a plurality of traces routed within said core logic area;
• a third test circuit constructed with a plurality of elements randomly placed within said core logic area;
• and
• a fourth test circuit constructed to mimic a data path within said core logic area, said fourth test circuit sharing a power source with at least one of said plurality of components within said core logic area.

A combination, comprising:

• an integrated circuit;
• and
• a testing system comprising:
• a signal generator;
• a plurality of ring oscillators responsive to said signal generator;
• and
• a signal analyzer responsive to said plurality of ring oscillators for dynamically measuring the effects of noise and cross-talk on said integrated circuit.

A method for dynamically testing the effects of signal noise and cross-talk on an integrated circuit having a core logic area, the method comprising:

• measuring an inactive operating frequency for each of a plurality of test circuits;
• measuring an active operating frequency for each of a plurality of test circuits;
• and
• analyzing said plurality of inactive operating frequencies and said plurality of active operating frequencies to determine the effects of signal noise and cross-talk on said integrated circuit.

A method comprising:

• measuring an inactive operating frequency of a first test circuit, said first test circuit having a first plurality of elements connected by a first plurality of traces, said first test circuit being constructed to mimic a data path within said core logic area, said inactive operating frequency representing an operating reference signal;
• measuring an inactive operating frequency of a second test circuit, said second test circuit having a second plurality of elements connected by a second plurality of traces, said second plurality of traces being routed within said core logic area;
• measuring an inactive operating frequency of a third test circuit, said third test circuit having a third plurality of elements connected by a third plurality of traces, said third plurality of elements being randomly located within said core logic area;
• and
• measuring an inactive operating frequency of a fourth test circuit, said fourth test circuit having a fourth plurality of elements connected by a fourth plurality of traces, said fourth test circuit being constructed to mimic a data path within said core logic area, said fourth test circuit sharing a power source with at least one of said plurality of components within said core logic area.

An integrated circuit testing apparatus, comprising at least two of the following circuits:

• a first test circuit operable to produce a first signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within an integrated circuit;
• a second test circuit operable to produce a second signal for determining at least one of a cross-talk effect on said plurality of components and the accuracy of an interconnect capacitance extraction value;
• a third test circuit operable to produce a third signal for determining at least one of an effect of system noise on the operational speed of said plurality of components and a maximum degradation expected for a logic path between said plurality of components;
• and
• a fourth test circuit operable to produce a fourth signal for determining an effect of power supply noise on a signal propagation delay within said plurality of components.