Methods for preventing cross-linking between multiple resists and patterning multiple resists
AssigneeMicron Technology, Inc.
InventorsBelford T. Coursey, Brent D. Gilgen
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Abstract
The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.
Claims81
A method of preventing cross-linking between resists on an intermediate semiconductor device structure comprising:
- providing a first resist;
- forming a separation layer substantially in contact with said first resist;
- and
- providing a second resist substantially in contact with said separation layer, wherein said separation layer is substantially non-reactive with said first resist and said second resist.
A method of preventing cross-linking between resists in an intermediate semiconductor device structure comprising:
- providing a first resist;
- forming an organic separation layer substantially in contact with said first resist;
- and
- providing a second resist substantially in contact with said organic separation layer, wherein said organic separation layer is substantially non-reactive with said first resist and said second resist.
A method of multi-layer resist patterning on an intermediate semiconductor device structure comprising:
- providing a first resist in openings located in an active region of said intermediate semiconductor device structure;
- forming an organic separation layer substantially in contact with said first resist;
- and
- providing a second resist substantially in contact with said organic separation layer.
A method of multi-layer resist patterning on an intermediate semiconductor device structure comprising:
- providing two resists separated by an organic separation layer, wherein a first resist is located below said organic separation layer and a second resist is located above said organic separation layer;
- polymerizing said second resist;
- patterning said second resist without substantially patterning or removing said first resist;
- removing said second resist and said organic separation layer;
- and
- removing said first resist.
An intermediate semiconductor device structure comprising:
- a substrate;
- a first resist on said substrate;
- a separation layer substantially in contact with said first resist;
- and
- a second resist on said substrate substantially in contact with said separation layer, wherein said separation layer is substantially non-reactive with said first resist and said second resist.
A container structure formed during the fabrication of a semiconductor device comprising:
- an active region comprising multiple openings in a portion of said active region;
- a first resist filling said multiple openings;
- an organic separation layer in contact with said first resist;
- and
- a second resist in contact with said organic separation layer, wherein said organic separation layer is substantially non-reactive with said first resist and said second resist.
An intermediate semiconductor device structure comprising:
- a first resist;
- an organic separation layer substantially in contact with said first resist;
- and
- a second resist substantially in contact with said organic separation layer, wherein said organic separation layer is substantially non-reactive with said first resist and said second resist.
Dependencies are inferred from the claim text.