Defect-free semiconductor templates for epitaxial growth and method of making same

A method for fabricating defect-free templates suitable for further epitaxial growth, wherein the defect-free templates are lattice-mismatched to a substrate, comprising the steps of:

• a) depositing a first epitaxial layer having a first thermal evaporation rate, wherein the first epitaxial layer is lattice-mismatched to the substrate, wherein a thickness of the first epitaxial layer exceeds a critical thickness required for a formation of defects, such that a plurality of defects are formed in the first epitaxial layer, such that a surface of said first epitaxial layer comprises at least one defect-free surface region, and at least one surface region in a vicinity of the defects;
• b) depositing a cap layer of a second material having a second thermal evaporation rate different from the first thermal evaporation rate, such that the cap layer is selectively deposited on the defect-free surface regions, and at least one of the surface regions in the vicinity of the defects remains uncovered;
• c) annealing a structure formed in step b) at a temperature and duration such that at least one of the surface regions in the vicinity of the defects that is uncovered evaporates, while defect-free surface regions covered by the cap layer remain unaffected, and at least one annealed region is formed;
• and
• d) depositing a third material, lattice-matched or nearly lattice matched to the first epitaxial layer, such that the third material overgrows both the cap layer and annealed regions of the first epitaxial layer, forming a defect-free epitaxial layer suitable as a template for further epitaxial growth.

A semiconductor device comprising at least one defect-free epitaxial layer, wherein at least a part of the device is manufactured by a method of fabrication of defect-free epitaxial layers on top of a surface of a first solid state material having a first thermal evaporation rate and a plurality of defects, wherein the surface comprises at least one defect-free surface region, and at least one surface region in a vicinity of the defects, the method comprising the steps of:

• a) depositing a cap layer comprising a second material having a second thermal evaporation rate different from the first thermal evaporation rate, wherein the cap layer is selectively deposited on the defect-free surface region, such that at least one of the regions of the surface in the vicinity of the defects remains uncovered;
• b) annealing a structure created in step a) at a temperature and duration such that at least one of the surface regions in the vicinity of the defects that is uncovered evaporates, while defect-free surface regions covered by the cap layer remain unaffected, and at least one annealed region is formed;
• and
• c) depositing a third material, lattice-matched or nearly lattice matched to the first solid state material, such that the third material overgrows both the cap layer and annealed regions of the first solid state material forming a defect-free epitaxial layer.

A semiconductor device comprising at least one defect-free epitaxial layer, wherein at least a part of the device is manufactured by a method of fabrication of defect-free epitaxial layers on a surface of a defect-containing first epitaxial layer, the method comprising the steps of:

• a) depositing the first epitaxial layer having a first thermal evaporation rate, wherein the first epitaxial layer is lattice-mismatched to a substrate, wherein a thickness of the first epitaxial layer exceeds a critical thickness required for a formation of defects, such that a plurality of defects are formed in the first epitaxial layer, wherein the surface of the first epitaxial layer comprises at least one defect-free surface region, and at least one surface region in a vicinity of the defects;
• b) depositing a cap layer of a second material having a second thermal evaporation rate different from the first thermal evaporation rate, such that the cap layer is selectively deposited on the defect-free surface regions, and at least one of the surface regions in the vicinity of the defects remains uncovered;
• c) annealing a structure formed in step b) at a temperature and duration such that at least one of the surface regions in the vicinity of the defects that is uncovered evaporates, while defect-free surface regions covered by the cap layer remain unaffected, and at least one annealed region is formed;
• and
• d) depositing a third material, lattice-matched or nearly lattice matched to the first epitaxial layer, such that the third material overgrows both the cap layer and annealed regions of the first epitaxial layer, forming a defect-free epitaxial layer suitable as a template for further epitaxial growth.

A high electron mobility transistor comprising:

• a) a substrate selected from the group consisting of a Si substrate and a GaAs substrate;
• b) a plastically relaxed Ga1−xInyAs layer grown on top of the substrate;
• and
• c) a defect-free Ga1−yInyAs layer grown on top of the plastically relaxed layer.

A high electron mobility transistor comprising:

• a) a substrate selected from the group consisting of a Si substrate and a GaAs substrate;
• b) a plastically relaxed Ga1−xInxAs layer grown on top of the substrate;
• and
• c) a defect-free Ga1−y−zInyAlzAs layer grown on top of the plastically relaxed Ga1−xInxAs layer.

A high electron mobility transistor comprising:

• a) a substrate selected from the group consisting of a Si substrate with a surface orientation (111), a SiC substrate, and a sapphire substrate;
• b) a plastically relaxed GaN layer grown on top of the substrate;
• and
• c) a defect-free GaN layer grown on top of the plastically relaxed GaN layer.

A high electron mobility transistor comprising:

• a) a substrate selected from the group consisting of a Si substrate with a surface orientation (111), a SiC substrate, and a sapphire substrate;
• b) a plastically relaxed Ga1−xInxN layer grown on top of the substrate;
• and
• c) a defect-free Ga1−yInyN layer grown on top of the plastically relaxed Ga1−xInxN layer.

An integrated circuit comprising:

• a) a Si substrate;
• b) a plastically relaxed Si1−xGex layer grown on top of the Si substrate;
• c) a defect-free Si1−yGey layer grown on top of the plastically relaxed Si1−xGex layer;
• and
• d) a thin pseudomorphically strained Si layer grown on top of the defect-free Si1−yGey layer.

A tilted cavity laser grown on an GaAs substrate, wherein an n-part of a cavity comprises:

• a) an epitaxial layer comprising a material selected from the group consisting of GaAs and Ga1-zAlzAs ;
• b) a plastically relaxed Ga1−xInxAs layer grown on top of the epitaxial layer;
• and
• c) a defect-free Ga1−yInyAs layer grown on top of the plastically relaxed Ga1−xInxAs layer.