Transparent continuous refresh RAM cell architecture
AssigneeBroadcom Corporation
InventorsCyrus Afghahi, Sami Issa
Life of this patent
Estimating the term…
Abstract
A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.
Claims2
In a memory circuit comprising a plurality of memory cells organized into columns and rows, said memory circuit having a first memory access cycle and a second memory access cycle, a method of refreshing the memory cells comprising:
- generating a first address used to write to first memory cells;
- generating a second address used to refresh second memory cells;
- comparing the first address with the second address;
- updating the second address using a predetermined algorithm if the first address is identical to the second address;
- writing first data to the first memory cells during a write phase of the first memory access cycle;
- and
- refreshing the second memory cells by reading second data from the second memory cells during a read phase of the second memory access cycle and writing the second data back to the second memory cells during a write phase of the second memory access cycle,
- wherein the write phase of the first memory access cycle substantially coincides with the read phase of the second memory access cycle.
Dependencies are inferred from the claim text.