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US 2003/0201838 A1Published application
Adaptive variable frequency clock system for high performance low power microprocessors
AssigneeIntel Corporation
InventorsSimon M. Tam, Stefan Rusu
Life of this patent
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Abstract
A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.
Claims30
A method comprising:
- driving a clock distribution network with a clock output from a phased locked loop (PLL);
- locking an adjustable clock generator with said phased locked loop;
- and
- substituting said adjustable clock generator for said PLL on said clock distribution network.
1 more element
A processor comprising:
- a processor core;
- clock switching logic coupled to said processor core, said clock switching logic to provide one of its clock inputs to provide as a core clock to said processor core;
- a phased lock loop (PLL) coupled to said clock switching logic, said PLL to input an initial clock signal to said clock switching logic;
- a controller coupled to said clock switching logic, said controller to select which of said clock inputs to said clock switching logic is said core clock;
- and
- an adjustable clock generator coupled to said controller, said adjustable clock generator to input an adjustable clock signal to said clock switching logic.
3 more elements
A system comprising:
- a memory coupled to a bus;
- a processor coupled to said bus, said processor comprising:
- a processor core;
- and
- a clock system comprising:
- clock switching logic coupled to said processor core, said clock switching logic to provide one of its clock inputs to provide as a core clock to said processor core;
- a phased lock loop (PLL) coupled to said clock switching logic, said PLL to input an initial clock signal to said clock switching logic;
- a controller coupled to said clock switching logic, said controller to select which of said clock inputs to said clock switching logic is said core clock;
- an adjustable clock generator coupled to said controller, said adjustable clock generator to input an adjustable clock signal to said clock switching logic;
- and
- a local feedback look to maintain said PLL in lock with an external system clock.
8 more elements
Dependencies are inferred from the claim text.