US 2003/0201815 A1Published application

2-level series-gated CML-based circuit with inductive components for optical communication

AssigneeQantec Communication, Inc.

InventorsJohn C. Tung, Minghao (Mary) Zhang

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Abstract

A fundamental building block of 2-level series-gated CML-based CMOS circuit which includes a number of inductive components for an electronic circuit system is disclosed that is capable of driving a significant level of external capacitive load at a high input clock frequency while providing a high level of output signal fidelity for optical data communication. The inductive components can be implemented as either separate inductors or as differentially coupled pairs forming a corresponding transformer element. The value of any particular inductive component is first selected to approximately resonate, at the desired output signal frequency, with its associated equivalent node capacitance but further adjusted to a final value that results in a minimum output waveform distortion for the particular application. Two exemplary cases of application, a Divide-by-2 counter and a Master Slave D-type Flip Flop are presented with associated time domain output waveforms.

Claims14

Dependent claims

A fundamental building block of 2-level series-gated Current Mode Logic (CML)-based Field Effect Transistor (FET) circuit for an electronic circuit system for optical communication, the fundamental building block comprising a number of successive levels of connected circuit structures in a direction from a ground terminal to a power supply terminal of said FET circuit, said number of successive levels of connected circuit structures further comprising:

a bias level circuit structure comprising a constant current source FET, called FET-Mc1, having its source connected to said ground terminal and its gate connected to an externally supplied control voltage VCS;
a first level circuit structure comprising two source coupled FETs, called FET-M1 and FET-M2, having their source terminals connected to a drain of said FET-Mc1 and their respective gates connected to a pair of externally supplied differential clock signals CLK and CLK;
and
a second level circuit structure comprising two sub-circuit structures, called SUB-C1 and SUB-C2, being connected to each other in a parallel manner and having their respective terminals nearest said ground terminal connected to drains of said FET-M1 and FET-M2, said SUB-C2 further comprising:
two cross coupled FETs, called FET-M5 and FET-M6, having their respective drain terminals further connected to SUB-C1 in said parallel manner and their source terminals connected to a drain of said FET-M2;
and
said SUB-C1 further comprising:
two source coupled FETs, called FET-M3 and FET-M4, having their respective drain terminals connected to SUB-C2 in said parallel manner, their source terminals connected to a drain of said FET-M1 and their respective gates connected to a pair of externally supplied differential data signals D and D;
a first serial load bridging a drain of said FET-M3 to said power supply terminal, said first serial load further comprising a serial connection of a resistor RA and an inductive component LA having an inductance value LAV;
a second serial load bridging a drain of said FET-M4 to said power supply terminal, said second serial load further comprising a serial connection of a resistor RB and an inductive component LB having an inductance value LBV;
and
said inductive components LA and LB being further magnetically coupled to each other thus forming a transformer structure with a coupling coefficient K
whereby the inclusion of said magnetically coupled inductive components LA and LB with the formation of said transformer structure allows the achievement of a higher load-driving capacity under a higher operating frequency by said electronic circuit system of which said 2-level series-gated CML-based FET circuit constitutes part of the speed-critical building blocks.

10 more elements

A fundamental building block of 2-level series-gated CML-based Bipolar Transistor (BPT) circuit for an electronic circuit system for optical communication, the fundamental building block comprising a number of successive levels of connected circuit structures in a direction from a ground terminal to a power supply terminal of said BPT circuit, said number of successive levels of connected circuit structures further comprising:

a bias level circuit structure comprising a constant current source BPT, called BPT-Qc1, having its emitter connected to said ground terminal and its base connected to an externally supplied control voltage VCS;
a first level circuit structure comprising two emitter coupled BPTs, called BPT-Q1 and BPT-Q2, having their emitter terminals connected to a collector of said BPT-Qc1 and their respective bases connected to a pair of externally supplied differential clock signals CLK and CLK;
and
a second level circuit structure comprising two sub-circuit structures, called SUB-C1 and SUB-C2, being connected to each other in a parallel manner and having their respective terminals nearest said ground terminal connected to collectors of said BPT-Q1 and BPT-Q2, said SUB-C2 further comprising:
two cross coupled BPTs, called BPT-Q5 and BPT-Q6, having their respective collector terminals further connected to SUB-C1 in said parallel manner and their emitter terminals connected to a collector of said BPT-Q2;
and
said SUB-C1 further comprising:
two emitter coupled BPTs, called BPT-Q3 and BPT-Q4, having their respective collector terminals connected to SUB-C2 in said parallel manner, their emitter terminals connected to a collector of said BPT-Q1 and their respective bases connected to a pair of externally supplied differential data signals D and D;
a first serial load bridging a collector of said BPT-Q3 to said power supply terminal, said first serial load further comprising a serial connection of a resistor RA and an inductive component LA having an inductance value LAV;
a second serial load bridging a collector of said BPT-Q4 to said power supply terminal, said second serial load further comprising a serial connection of a resistor RB and an inductive component LB having an inductance value LBV;
and
said inductive components LA and LB being further magnetically coupled to each other thus forming a transformer structure with a coupling coefficient K
whereby the inclusion of said magnetically coupled inductive components LA and LB with the formation of said transformer structure allows the achievement of a higher load-driving capacity under a higher operating frequency by said electronic circuit system of which said 2-level series-gated CML-based BPT circuit constitutes part of the speed-critical building blocks.

10 more elements

Dependencies are inferred from the claim text.