Pulsed signal transition delay adjusting circuit

An integrated circuit comprising:

• an input node for receiving an input signal;
• a first node;
• a first logic circuit coupled between the input node and the first node, the first logic circuit coupled between a first voltage and a second voltage;
• a second logic circuit coupled to the first node and for generating an output signal of a first level when a voltage at the first node is below a predetermined voltage, and of a second level otherwise;
• a first signal terminal for receiving a first delay control signal for a rising delay of the output voltage with respect to the input signal;
• a first capacitor coupled between the first signal terminal and a second node;
• a first switch coupled between the first node and the second node, the first switch controlled by the output signal;
• a first precharge circuit controlled by the output signal for selectively precharging the second node between the first switch and the first capacitor;
• a second signal terminal for receiving a second delay control signal for a falling delay of the output voltage with respect to the input signal;
• a second capacitor coupled between the second signal terminal and a third node;
• a second switch coupled between the first node and the third node, the second switch controlled by the output signal.