Duty cycle correction based frequency multiplier

Abstract

A frequency multiplier and method of frequency multiplication overcome the shortcomings of those frequency multiplication systems and methods that utilize a phase locked loop or a delay locked loop, and occupy smaller chip area and consume less power when embodied in an integrated circuit. A first duty cycle correction circuit receives a first signal and generates a second signal, the frequency of which is the same as that of the first signal and the duty cycle of which is 50:50. An edge detector detects edges of the second signal and generates a third signal corresponding to the detected edges. In an optional embodiment, a second duty cycle correction circuit receives the third signal and generates a fourth signal, the frequency of which is the same as that of the third signal and the duty cycle of which is 50:50. Since the frequency multiplier and the method of multiplying frequencies utilize relatively simple circuits without the need for using a phase locked loop or a delay locked loop, it is possible to prevent the problems of jitter and false locks.

Dependencies are inferred from the claim text.