Method and apparatus for asynchronously controlling a high-capacity domino pipeline

A domino logic circuit that operates asynchronously, comprising:

• a pipeline comprised of a number of stages containing domino logic, including a present stage that receives one or more inputs from a prior stage and that generates one or more outputs for a next stage;
• and
• a control circuit for the present stage that is configured to ensure that the present stage enters a precharging state before entering an evaluation state in which one or more inputs of the present stage are used to generate one or more outputs;
• wherein the control circuit receives a prior control signal from the prior stage and sends a present control signal to the next stage;
• wherein the control circuit for the present stage is configured so that a minimum cycle time between successive evaluation states is six gate delays;
• wherein the control circuit for the present stage feeds an evaluation signal into domino logic in the present stage, which causes the domino logic in the present stage to enter the evaluation state;
• wherein the control circuit for the present stage feeds a precharging signal into the present stage, which causes the domino logic in the present stage to enter the precharging state;
• and
• wherein if the evaluation signal and the precharging signal are not asserted, the domino logic in the present stage enters a hold state in which the outputs of the domino logic do not change.

A computer system including domino logic circuitry that operates asynchronously, comprising:

• a processor;
• a main memory;
• a pipeline comprised of a number of stages containing domino logic, including a present stage that receives one or more inputs from a prior stage and that generates one or more outputs for a next stage;
• and
• a control circuit for the present stage that is configured to ensure that the present stage enters a precharging state before entering an evaluation state in which one or more inputs of the present stage are used to generate one or more outputs;
• wherein the control circuit receives a prior control signal from the prior stage and sends a present control signal to the next stage;
• and
• wherein the control circuit for the present stage is configured so that a minimum cycle time between successive evaluation states is six gate delays.

A method for asynchronously controlling a number of stages of domino logic gates, comprising:

• receiving a prior control signal from a prior stage indicating that the prior stage is in an evaluation state in which the prior stage generates at least one output for a present stage;
• and
• in response to the prior control signal,
• causing domino logic within the present stage to enter the evaluation state, so that domino logic within the present stage evaluates at least one input received from the prior stage to produce at least one output for a next stage, and
• causing the prior stage returns to a precharging state, whereby the domino logic within the prior stage precharges before entering a subsequent evaluation state;
• wherein a minimum cycle time between successive evaluation states is six gate delays.