Programmable logic device with hierarchical interconnection resources

An integrated circuit comprising:

• a plurality of super-regions of logic disposed on the integrated circuit in a two-dimensional array of rows and columns, each of the super-regions including:
• a plurality of regions of logic, each of the regions including a plurality of subregions of logic, each of the subregions connected to perform a set of predefined logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals;
• and
• a plurality of input interconnection conductors associated with each of said regions configured to convey signals to the subregions in the associated region so that said signals on said input interconnection conductors are available for application to said subregions in the associated region as said input signals;
• a plurality of inter-region interconnection conductors connected to said input interconnection conductors and configured to convey signals to the regions in the super-region so that said signals on said inter-region interconnection conductors are available for application to said subregions in the super-region as said input signals;
• a plurality of horizontal inter-super-region interconnection conductors associated with each of said rows and configured to convey signals to, from, and between super-regions in the associated row, said horizontal inter-super-region interconnection conductors connected to said input interconnection conductors;
• a plurality of vertical inter-super-region interconnection conductors associated with each-of said columns and configured to convey signals to, from, and between super-regions in the associated column, said vertical inter-super-region interconnection conductors connected to said input interconnection conductors;
• a first plurality of logic connectors configured to apply signals on said horizontal and vertical inter-super-region interconnection conductors to the subregions in a super-region adjacent to said inter-super-region conductors as said input signals by routing through the input conductors associated with said subregions and without routing through any of said inter-region interconnection conductors;
• a second plurality of logic connectors configured to apply signals on said inter-region interconnection conductors to each of said subregions in a region as said input signals by routing through the input conductors associated with said subregions;
• and
• a third plurality of logic connectors configured to interconnect said horizontal and vertical inter-super-region interconnection conductors.

An architecture for a logic device comprising:

• a plurality of super-regions of logic disposed on the logic device in a two-dimensional array of rows and columns, each of the super-regions including:
• a plurality of regions of logic, each of the regions including a plurality of subregions of logic, each of the subregions connected to perform a set of predefined logic functions on a plurality of input signals applied to the subregion to produce an output signal which is indicative of the result of performance of the logic function on the input signals;
• region-feeding interconnection conductors associated with each of said regions and configured to convey signals to all of the subregions in the associated region for application to said subregions as said input signals, said region-feeding interconnection conductors running substantially parallel to a first axis of said two-dimensional array;
• and
• a plurality of inter-region interconnection conductors associated with each of said regions and configured to convey signals for application to any of said region-feeding interconnection conductors in the associated region, said inter-region interconnection conductors running substantially parallel to a second axis of said two-dimensional array that is substantially perpendicular to the first axis, routing through a region-feeding interconnection conductor associated with a subregion being the sole routing available on said device for applying a signal from said inter-region interconnection conductors to that subregion as one of said input signals;
• and
• a plurality of inter*super-region interconnection conductors configured to convey signals for application to said inter-region interconnection conductors, said inter*super-region interconnection conductors running substantially parallel to the first axis of said two-dimensional array, routing through an inter-region interconnection conductor associated with a super-region and a region-feeding interconnection conductor associated with a subregion in that super-region being the sole routing available on said device for applying a signal from said inter-super-region interconnection conductors to that subregion as one of said input signals.

An integrated circuit device comprising:

• a two-dimensional array of intersecting rows and columns of super-regions of logic;
• a plurality of horizontal inter-super-region interconnection conductors associated with each of said rows;
• a plurality of vertical inter-super-region interconnection conductors associated with each of said columns;
• each of said super-regions including a plurality of intersecting rows and columns of regions of logic with horizontal and vertical inter-region interconnection conductors, wherein each of said regions includes a plurality of subregions of logic that are connected to perform a set of predefined logic functions on input signals applied to said subregion to produce an output signal of said subregion;
• logic connectors associated with each of said super-regions configured to interconnect said inter-region interconnection conductors of said super-region to inter-super-region interconnection conductors associated with the row and column that include said super-region;
• a plurality of local conductors associated with each of said regions configured to bring signals from said inter-region interconnection conductors into said region, the subregions in each region being disposed so that the local conductors associated with that region can extend adjacent to all of the subregions in that region by running substantially parallel to a first axis of said two-dimensional array;
• subregion input conductors configured to apply signals on said local conductors to the subregions associated with said local conductors as said input signals to the subregions by running substantially parallel to a second axis of said two-dimensional array that is substantially perpendicular to the first axis, routing through a local conductor and a subregion input conductor associated with a subregion being the sole routing available on said integrated circuit for applying a signal from any of said inter-region interconnection conductors to that subregion as one of said input signals;
• and
• subregion output conductors configured to apply said output signal to one of said local conductors associated with said subregion by running substantially parallel to said second axis of said two-dimensional array, routing through a subregion output conductor associated with a subregion and a local conductor being the sole routing available on said integrated circuit for applying an output signal from said subregion to any of said inter-region interconnection conductors.