Line segmentation in programmable logic devices having redundancy circuitry

A method of segmenting programmable interconnect lines in a programmable logic device comprising a segmentation buffer, a plurality of redundant logic array blocks, a first plurality of logic array blocks on a first side of the segmentation buffer and between the segmentation buffer and the plurality of redundant logic array blocks, and a second plurality of logic array blocks on a second side of the segmentation buffer and not between the segmentation buffer and the plurality of redundant logic array blocks, the method comprising:

• determining whether a defective logic array block exists;
• and
• if no defective logic array block exists, making no changes to the segmentation buffer;
• else
• determining a location of a defective logic array block;
• and
• if the location of the defective logic array block is in the first plurality of logic array blocks, making no changes to the segmentation buffer;
• else
• determining the location of an active line driver for a line coupled to the segmentation buffer;
• and
• if the location of the active line driver is in a logic array block next to the second side of segmentation buffer, setting the segmentation buffer to drive signals from the first plurality of logic array blocks to the second plurality of logic array blocks;
• else
• setting the segmentation buffer to drive signals from the second plurality of logic array blocks to the first plurality of logic array blocks.

A programmable logic device comprising:

• a first plurality of logic array blocks, the first plurality of logic array blocks comprising a first logic array block and a second logic array block;
• a first programmable interconnect line coupled to a first terminal of a segmentation buffer and programmably coupled to the first logic array block;
• and
• a second programmable interconnect line coupled to a second terminal of the segmentation buffer and programmably coupled to the second logic array block,
• wherein the segmentation buffer is capable of being configured to provide an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.