PLL semiconductor device with testability, and method and apparatus for testing same

Abstract

On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (P×N+A) 22 wherein each of P, N and A is an integer, A is variable and A<N, a phase comparator 23, and a charge pump 24. A low pass filter 25 having been confirmed to have standard characteristics is externally added to the semiconductor device 20 to construct a PLL circuit to be tested. The frequency divider 22 is of a pulse swallow type and has a control input for setting the integer A at ones in the vicinity of a value in normal use by user. The control input is connected to external terminals D0 and D1 of the semiconductor device 20 for simplifying a test. The semiconductor device 20 is judged whether it is acceptable or not in quality by checking whether or not the PLL circuit enters into a locked state within a given period in each cases of A=A1 and A=A2, where A1<A0<A2 and A0 is a value in normal use by user.

Dependencies are inferred from the claim text.