Impedance enhancement circuit for CMOS low-voltage current source

A current source with a current source output, capable of driving a large capacitive load and capable of driving Printed Wiring Board signal lines, and maintaining high impedance over a wide range of voltage at said output, comprising:

• an FET current source driver, having a gate, a source, and a drain, which operates in both a saturated and a linear region of the FET operating region,
• a voltage control mechanism with an input and an output, said output coupled to said gate of said FET current source driver, which, for the saturated region of operation of said FET current source driver, provides a constant voltage to said gate of said FET current source driver, and which, for the linear region of operation of said FET current source driver, provides a changing voltage to said gate of said FET current source driver to provide a substantially constant current from said FET current source driver in both the saturated region of operation and a portion of the linear region of operation;
• and
• a feedback connected between said current source output and said input of said voltage control mechanism, said feedback utilized by said voltage control mechanism to control the voltage provided to said gate of said FET current source driver.

A current source with a current source output, capable of driving a Printed Wiring Board signal or an electrical transmission line signal over a wide range of voltage, comprising:

• a first FET, having a drain coupled to said current source output, a gate, and a source coupled to a first voltage supply;
• a second FET, having a gate and a drain coupled to said gate of said first FET, and a source;
• a first current bias source;
• a load;
• a third FET having a source coupled to said first current bias source, a gate coupled to said current source output, and a drain coupled to said source of said second FET, and further coupled to said load;
• a voltage reference;
• a fourth FET having a source coupled to said first current bias source, a gate coupled to said voltage reference, and a drain;
• a fifth FET having a source coupled to said first voltage supply, and a gate and a drain coupled to said drain of said fourth FET;
• a sixth FET, having a gate coupled to said gate of said fifth FET, a source coupled to said first voltage supply, and a drain coupled to said gate of said second FET;
• and
• a second current bias source, coupled to said gate of said first FET.

A method of providing a current source with an output capable of producing a high impedance output for driving a Printed Wiring Board signal over a wide range of output voltage, including at least a portion of a linear range of operation of a driver FET, comprising the steps of:

• coupling a drain of said driver FET to said output;
• coupling a source of said driver FET to a first supply voltage;
• and
• controlling a gate of said driver FET to maintain a substantially constant current through the output as a drain to source voltage of said driver FET varies, including when the drain to source voltage is in the saturated region of operation and when the drain to source voltage is in at least a portion of the linear range of operation of said driver FET.