Multiple chips bonded to packaging structure with low noise and multiple selectable functions

A package for semiconductor chips including:

• a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which are selected from:
• a) a power bus and a ground bus, and
• b) a power plane and a ground plane located within the printed circuit board,
• solder connections between the printed circuit board and a chip overlying the printed circuit board in a flip chip connection,
• a bypass capacitor with a first terminal and a second terminal, and
• the first terminal of the bypass capacitor being connected to the power structure and the second terminal being connected to the ground structure.

A method of forming a chip package for a semiconductor chip including the steps as follows:

• forming a first printed circuit board having a top surface and a bottom surface including a power plane and a ground plane located within the first printed circuit board,
• forming a second printed circuit board having a top surface and a bottom surface,
• bonding a first chip to the top surface of the first printed circuit board and bonding a second chip to the bottom surface of the first printed circuit board in a flip chip connection,
• bonding a third chip to the bottom surface of the second printed circuit board in a flip chip connection, and
• bonding the chips to the printed circuit boards by means selected from the following:
• a) solder balls, and
• b) gold bumps.

A chip package for a semiconductor chip including:

• a first printed circuit board having a top surface and a bottom surface including a power plane and a ground plane located within the first printed circuit board,
• a second printed circuit board having a top surface and a bottom surface,
• a first chip bonded to the top surface of the first printed circuit board and a second chip bonded to the bottom surface of the first printed circuit board in a flip chip connection,
• a third chip bonded to the bottom surface of the second printed circuit board in a flip chip connection,
• a bypass capacitor with a first terminal and a second terminal,
• the first terminal of the bypass capacitor connected to the power plane and the second terminal of the, bypass capacitor connected to the ground plane, and
• the bottom surface of the first printed circuit board interconnected to the top surface of the second printed circuit board with a solder ball.

A method of forming a chip package for semiconductor chips including the stops as follows:

• forming a printed circuit board with a window therethrough having a length and a width and a toy) surface and a bottom surface,
• semiconductor chips including a primary chip and a secondary chip,
• forming, bonded connections between the top surface of the printed circuit board and the primary chip, with the primary chip overlying the window and which extends transversely across the width of the window,
• locating, the secondary chip suspended within the window and forming bonded connections between the secondary semiconductor chip and the primary chip in a chip-on-chip connection.

A chip package for semiconductor chips including the steps as follows:

• at printed circuit board with at window therethrough having a length and a width and a top surface and a bottom surface,
• semiconductor chips including a primary chip and a secondary chip,
• bonded connections between the top surface of the printed circuit board and the primary chip, with the primary chip overlying the window and which extends transversely across the width of the window,
• the secondary chip being suspended within the window and having bonded connections between the secondary semiconductor chip and the primary chip in a chip-on-chip connection.

A method of forming a chip package for semiconductor chips including the steps as follows:

• providing a substrate having a top surface and a bottom surface,
• semiconductor chips including a primary chip and a secondary chip, the primary chip having a bottom surface and the secondary chip having a top surface,
• forming bonded chip-on-chip connections between the top surface of the secondary chip and the bottom surface of the primary chip, and
• forming bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip leaving, space between the secondary chip and the printed circuit board.

A chip package for semiconductor chips including:

• a substrate having a top surface and a bottom surface,
• semiconductor chips including a primary chip and a secondary chip, the primary chip having a bottom surface and the secondary chip having a top surface,
• bonded chip-on-chip connections between the top surface of the secondary chip and the bottom surface of the primary chip, and
• bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip leaving space between the secondary chip and the printed circuit board.

A chip package for semiconductor chips comprising:

• a printed circuit board with a top surface and a window therethrough,
• at least two primary semiconductor chips each of which only partially overlies the window connected to the top surface of the printed circuit board by solder connections,
• a suspended secondary semiconductor chip located within the window, and
• the suspended semiconductor chip being connected to at least of the two primary chips overlying the window in a chip-on-chip connection.

A method of forming a chip package for a semiconductor chip including the steps as follows:

• forming a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which include:
• a) a power bus and a ground bus, and
• b) a power plane and a ground plane located within the printed circuit board,
• forming solder connections between the printed circuit board and a plurality of chips overlying the printed circuit board in flip chip connections,
• providing a bypass capacitor with a first terminal and a second terminal, and
• connecting the first terminal of the bypass capacitor to the power structure and connecting the second terminal of the bypass capacitor to the ground structure, and
• forming optional pads for connection to optional solder balls for functional selection.

A chip package for a semiconductor chip including:

• a printed circuit board having;
• a top surface and a bottom surface including a power structure and a ground structure which include:
• a) a power bus and a ground bus, and
• b) a power plane and a ground plane located within the printed circuit board,
• solder connections between the printed circuit board and a plurality of chips overlying the printed circuit board in flip chip connections,
• a bypass capacitor with a first terminal and a second terminal, and
• connecting the first terminal of the bypass capacitor to the power structure and connecting;
• the second terminal of the bypass capacitor to the ground structure, and
• optional pads for connection to optional solder balls for functional selection.