Semiconductor device and manufacturing method thereof
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei Yamazaki, Hideomi Suzawa, Hirokazu Yamagata
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Abstract
In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions (213, 214) of a pixel TFT is caused to overlap with second wirings (source line or drain line) (154, 157). Additionally, a first interlayer insulating film (149) and a second interlayer insulating film (150c) are disposed between the gate electrode and the second wirings (154, 157) so as to decrease a parasitic capacitance.
Claims31
A semiconductor device comprising:
- a first wiring formed on an insulating surface;
- a first interlayer insulating film formed on said first wiring;
- a second interlayer insulating film formed in contact with a part of said first interlayer insulating film;
- and
- a second wiring formed on said first and second interlayer insulating films;
- wherein said first and second interlayer insulating films are laminated in a region where said first wiring overlaps with said second wiring.
A semiconductor device having at least one TFT on an insulating surface, said TFT comprising:
- a first interlayer insulating film, a second interlayer insulating film and a second wiring formed over a first wiring, and
- a gate insulating film, said interlayer insulating film and said second wiring formed over a source region or a drain region of said TFT.
A semiconductor device including at least a TFT on an insulating surface, said TFT comprising:
- a second wiring is formed over a first wiring with a first interlayer insulating film and second interlayer insulating films interposed therebetween.
A semiconductor device including at least a pixel circuit and a driving circuit for controlling said pixel circuit, said pixel circuit and said driving circuit formed over a same substrate, comprising:
- a pixel TFT forming said pixel circuit;
- a channel region of said pixel TFT overlapping with a part of a first wiring with a gate insulating film interposed therebetween;
- wherein said part of said gate wiring overlaps with a second wiring with a plurality of insulating films, each having an etching rate different each other.
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first wiring on an insulating surface;
- forming a first interlayer insulating film over said first wiring;
- forming a second interlayer insulating film on said first interlayer insulating film;
- selectively removing a part of said second interlayer insulating film;
- and
- forming a second wiring on said second interlayer insulating film that overlaps with said first wiring.
A method of manufacturing a semiconductor device including at least one TFT on an insulating surface, said method comprising:
- forming an active layer on the insulating surface;
- forming a gate insulating film on said active layer;
- introducing an n-type impurity element or a p-type impurity element into a portion of said active layer, thereby forming a source region or a drain region;
- forming a first interlayer insulating film over a gate wiring and a gate electrode;
- forming a second interlayer insulating film on said first interlayer insulating film;
- etching said second interlayer insulating film, thereby eliminating said second interlayer insulating film disposed over said source region or said drain region;
- etching said first interlayer insulating film and said gate insulating film, thereby forming a contact hole that reaches said source region or said drain region;
- and
- forming a second wiring in contact with said source region or said drain region, said second wiring disposed on said second interlayer insulating film that overlaps with said gate electrode.
A method of manufacturing a semiconductor device including at least a pixel circuit and driving circuit for controlling said pixel circuit, each disposed on a same substrate, said method comprising:
- forming an active layer on an insulating surface;
- forming a gate insulating film on said active layer;
- forming a gate wiring and a gate electrode on said gate insulating film;
- a fourth step of adding an n-type impurity element or a p-type impurity element to a part of said active layer, thereby forming an n-type impurity region or a p-type impurity region;
- forming a first interlayer insulating film over said gate wiring and said gate electrode;
- selectively forming a second interlayer insulating film on said first interlayer insulating film that overlaps with said gate electrode;
- etching said first interlayer insulating film and said gate insulating film, thereby forming a contact hole that reaches said n-type impurity region or said p-type impurity region;
- and
- forming a second wiring in contact with said n-type impurity region or said p-type impurity region, said second wiring disposed on said second interlayer insulating film that overlaps with said gate electrode.
A method of manufacturing a semiconductor device including at least a pixel circuit and driving circuit for controlling said pixel circuit, each disposed on a same substrate, said method comprising the steps of:
- forming an active layer on an insulating surface;
- forming a gate insulating film on said active layer;
- forming a gate wiring and a gate electrode on said gate insulating film;
- introducing an n-type impurity element or a p-type impurity element into a portion of said active layer, thereby forming an n-type impurity region or a p-type impurity region;
- forming a first interlayer insulating film over said gate wiring and said gate electrode;
- etching said first interlayer insulating film and said gate insulating film, thereby forming a contact hole that reaches said n-type impurity region or said p-type impurity region;
- selectively forming a second interlayer insulating film on said first interlayer insulating film;
- and
- forming a second wiring in contact with said n-type impurity region or said p-type impurity region, said second wiring disposed on said second interlayer insulating film that overlaps with said gate electrode.
Dependencies are inferred from the claim text.