Spacer patterned, high dielectric constant capacitor
AssigneeMicron Technology, Inc.
InventorDarwin A. Clampitt
Life of this patent
Estimating the term…
Abstract
A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer width pillars or having edges without sharp corners that lead to electric field breakdown of the high dielectric constant material. The combination of high dielectric constant material in a memory cell along with a relatively large surface area conductive structure is achieved through the use of a buffer material as caps on the thin edge surfaces of the relatively large surface area conductive structures to dampen or eliminate the intense electric field which would be generated at the corners of the structures during the operation of the memory cell capacitor had the caps not been present.
Claims18
A capacitor, comprising:
- a large surface area electrode in electrical communication with a drain region of a semiconductor substrate, said large surface area electrode including at least one protruding edge;
- a buffer material comprising insulative material on said at least one protruding edge;
- a dielectric film coating exposed surfaces of said large surface area electrode and said buffer material;
- and
- another electrode spaced apart from said large surface area electrode by said dielectric film.
A semiconductor DRAM comprising:
- a large surface area conductive structure in electrical communication with a drain region of a semiconductor substrate and including at least one protruding region;
- a buffer material comprising insulative material on an edge of said at least one protruding region;
- a dielectric film coating exposed regions of said large surface area conductive structure and said buffer material;
- and
- another conductive structure spaced apart from said large surface area conductive structure by said dielectric film.
A capacitor, comprising:
- a large surface area electrode in electrical communication with a drain region of a semiconductor substrate, said large surface area electrode including at least one protruding edge;
- a buffer material on said at least one protruding edge and configured to at least partially dampen an electric field at said at least one protruding edge, prevent an electric field from forming at said at least one protruding edge, or reduce or eliminate the effects of an electrical field present at said at least one protruding edge;
- a dielectric film coating exposed areas of said large surface area electrode and said buffer material;
- and
- another electrode spaced apart from said large surface area electrode by said dielectric film.
A semiconductor DRAM comprising:
- a large surface area conductive structure in electrical communication with a drain region of a semiconductor substrate and including at least one protruding region;
- a buffer material on at least one edge of said at least one protruding region and configured to at least partially dampen an electric field at said at least one edge, prevent an electric field from forming at said at least one edge, or reduce or eliminate the effects of an electrical field present at said at least one edge;
- a dielectric film over said large surface area conductive structure and said buffer material;
- and
- another conductive structure spaced apart from said large surface area conductive structure by said dielectric film.
Dependencies are inferred from the claim text.