Semiconductor capacitive element, method for manufacturing same and semiconductor device provided with same

A method for manufacturing a semiconductor capacitive element which uses wirings buried in an interlayer dielectric on a semiconductor substrate as electrodes, said method comprising:

• a lower layer wiring trench forming process in which, after a first etching stopper film and a first interlayer dielectric have been sequentially formed on said semiconductor substrate, each of said first interlayer dielectric and said first etching stopper film in a first region corresponding to a multi-layer wiring forming portion and each of said first interlayer dielectric and said first etching stopper film in a second region corresponding to a capacitor forming portion on said semiconductor substrate are selectively etched to form first and second lower layer wiring trenches,
• a lower layer conductive film forming process of forming a lower layer wiring in said first lower layer wiring trench in said first region corresponding to said multi-layer wiring forming portion and, at a same time, of forming a lower electrode in said second lower layer wiring trench in said second region corresponding to said capacitor forming portion;
• a via hole forming process in which, after a second etching stopper film and a second interlayer dielectric have been sequentially formed on said first interlayer dielectric, said second interlayer dielectric and said second etching stopper film in said first region corresponding to said multi-layer wiring forming portion are selectively etched to form a first via hole and, at a same time, said second interlayer dielectric in said second region corresponding to said capacitor forming portion is selectively etched to form a second via hole to allow said second etching stopper film to be exposed;
• and
• a via plug forming process of forming a first via plug in said first via hole in said first region corresponding to said multi-layer wiring forming portion and, at a same time, of forming a second via plug serving as an upper electrode in said second via hole in said second region corresponding to said capacitor forming portion.

A method for manufacturing a semiconductor capacitive element which uses wirings buried in an interlayer dielectric on a semiconductor substrate as electrodes, said method comprising:

• a lower layer wiring trench forming process in which, after a first etching stopper film and a first interlayer dielectric have been sequentially formed on said semiconductor substrate, each of said first interlayer dielectric and said first etching stopper film in a first region corresponding to a multi-layer wiring forming portion and each of said first interlayer dielectric and said first etching stopper film in a region corresponding to a capacitor forming portion on said semiconductor substrate are selectively etched to form a first lower layer wiring trench and a second lower layer wiring trenches, respectively;
• a lower layer conductive film forming process of forming a lower layer wiring in said first lower layer wiring trench in said first region corresponding to said multi-layer wiring forming portion and at a same time, of forming a lower electrode in said second lower layer wiring trench in said second region corresponding to said capacitor forming portion;
• an upper layer wiring trench forming process in which, after a second etching stopper film, a second interlayer dielectric, a third etching stopper film, and a third interlayer dielectric have been sequentially formed on said first interlayer dielectric, each of said third interlayer dielectric and said etching stopper film in said first region corresponding to said multi-layer wiring forming portion and each of said third interlayer dielectric and said etching stopper film in said second region corresponding to said capacitor forming portion are selectively etched to form a first upper layer wiring trench and a second upper layer wiring trench, respectively;
• a via hole forming process of selectively etching said second interlayer dielectric and said second etching stopper film in said first region corresponding to said multi-layer wiring forming portion to form a first via hole so that said first via hole is connected to said first upper layer wiring trench, and selectively etching said second interlayer dielectric in said second region corresponding to said capacitor forming portion to allow said second etching stopper film to be exposed and to form a second via hole so that said second via hole is connected to said second upper layer wiring trench;
• and
• a conductive film forming process of simultaneously forming a first via plug and an upper layer wiring, respectively, in said first via hole and in said first upper layer wiring trench in said first region corresponding to said multi-layer wiring forming portion and, at a same time, of simultaneously forming a second via plug and an upper layer wiring, both being used as upper electrodes, respectively, in said second via hole and in said second upper layer wiring trench in said second region corresponding to said capacitor forming section.

A semiconductor device provided with a semiconductor capacitive element using wirings buried in an interlayer dielectric on a semiconductor substrate as electrodes, said semiconductor capacitive element comprising:

• a lower electrode being buried in a first interlayer dielectric formed on said semiconductor substrate;
• an upper electrode being buried in a second interlayer dielectric formed via an etching stopper film on said first interlayer dielectric;
• and
• a capacitive insulating film made up of said etching stopper film being formed only in a region being sandwiched between said upper electrode and said lower electrode.