DRAM with vertical transistors and deep trench capacitors

A folder bitline DRAM with vertical transistors, deep trench capacitors and borderless bitline contact windows, comprising:

• a substrate;
• a plurality of wordlines disposed on the substrate;
• a plurality of deep trench capacitors disposed in the substrate, wherein the deep trench capacitors belonging to different rows are arranged with a shift, and two wordlines leap over each deep trench capacitor;
• a plurality of bitlines disposed over the wordlines and perpendicular to the wordlines;
• each active region corresponding to the bitlines and comprising two wordlines which leap different deep trench capacitors and functioned as gates, wherein each two adjacent active regions corresponding to two adjacent bitlines are arranged with a shift;
• an insulating layer disposed between each gate and each deep trench capacitor;
• a common drain disposed between the two gates belonging to the two wordlines which leap over different deep trench capacitors;
• a deep trench capacitor disposed below each gate;
• a contact window connected to the common drain and bitline;
• an ion doped layer disposed between each insulating layer and each deep trench capacitor;
• a source disposed on a sidewall of each ion doped layer in the substrate;
• a gate insulating layer disposed on a sidewall of a portion of each gate, wherein the source is located on one side of the gate insulating layer;
• and
• a shallow trench isolation disposed outside the active region.