Method of forming memory arrays based on a triple-polysilicon source-side injection non-volatile memory cell

A method of manufacturing first and second semiconductor memory array configurations, each array configuration including a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal, the method comprising:

• forming a plurality of rows of continuous program gate lines, each row of program gate line forming the program gate terminals of the cells along the row, the program gate lines being from a second layer polysilicon;
• forming a plurality of rows of continuous select gate lines, each row of select gate line forming the select gate terminals of the cells along the row, the select gate lines being from a third layer polysilicon;
• forming a plurality of rows of continuous source lines, each source line forming the source regions of the cells along the row, the source lines being from diffusion;
• wherein the first array configuration is obtained by:
• forming a plurality of local bitlines, the cells along each column being divided into a predesignated number of groups, the drain regions of the cells in each group being connected to one of the local bitlines extending across the cells in the group of cells;
• and
• forming a plurality of global bitlines along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the two columns of cells, wherein the local bitlines are from a first layer metal and the global bitlines are from a second layer metal.