Insulated gate semiconductor device

An insulated gate semiconductor device comprising:

• a first semiconductor layer of a first conductivity type;
• a plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the first semiconductor layer;
• at least one third semiconductor layer of the first conductivity type formed in a surface area of each of the second semiconductor layers;
• a plurality of first main electrodes connected to the second semiconductor layers and the third semiconductor layer, respectively;
• a fourth semiconductor layer formed on a bottom of the first semiconductor layer;
• a second main electrode connected to the fourth semiconductor layer;
• a control electrode formed on a surface of each of the second semiconductor layers, the third semiconductor layer, and the first semiconductor layer with a gate insulation film interposed therebetween;
• and
• at least one fifth semiconductor layer of the second conductivity type provided in the first semiconductor layer and connected to at least one of the plurality of second semiconductor layers, the fifth semiconductor layer having impurity concentration that is lower than that of the second semiconductor layers,
• wherein capacitance between the control electrode and the second main electrode decreases when a voltage applied to the second main electrode is low and the capacitance remains constant or increases when the voltage is high.

An insulated gate semiconductor device comprising:

• a first semiconductor layer of a first conductivity type;
• a plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the first semiconductor layer;
• at least one third semiconductor layer of the first conductivity type formed in a surface area of each of the second semiconductor layers;
• a plurality of first main electrodes connected to the second semiconductor layers and the third semiconductor layer, respectively;
• a fourth semiconductor layer formed on a bottom of the first semiconductor layer;
• a second main electrode connected to the fourth semiconductor layer;
• a control electrode formed on a surface of each of the second semiconductor layers, the third semiconductor layer, and the first semiconductor layer with a gate insulation film interposed therebetween;
• and
• at least one fifth semiconductor layer of the second conductivity type provided in the first semiconductor layer and connected to at least one of the plurality of second semiconductor layers, the fifth semiconductor layer having impurity concentration that is lower than that of the second semiconductor layers,
• wherein capacitance between the control electrode and the second main electrode starts to increase when a voltage applied to the second main electrode is one-third to two-thirds of a rated voltage.

An insulated gate semiconductor device comprising:

• a first semiconductor layer of a first conductivity type;
• a plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the first semiconductor layer;
• at least one third semiconductor layer of the first conductivity type formed in a surface area of each of the second semiconductor layers;
• a plurality of first main electrodes connected to the second semiconductor layers and the third semiconductor layer, respectively;
• a fourth semiconductor layer formed on a bottom of the first semiconductor layer;
• a second main electrode connected to the fourth semiconductor layer;
• a control electrode formed on a surface of each of the second semiconductor layers, the third semiconductor layer, and the first semiconductor layer with a gate insulation film interposed therebetween;
• and
• at least one fifth semiconductor layer of the second conductivity type provided in the first semiconductor layer and connected to at least one of the plurality of second semiconductor layers, the fifth semiconductor layer having impurity concentration that is lower than that of the second semiconductor layers,
• wherein the fifth semiconductor layer of the second conductivity type is completely depleted when a voltage applied to the second main electrode is one-third to two-thirds of a rated voltage.

An insulated gate semiconductor device comprising:

• a first cell including a plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of a first semiconductor layer of a first conductivity type, at least one third semiconductor layer of the first conductivity type formed in a surface area of each of the second semiconductor layers, and a plurality of first main electrodes connected to the plurality of second semiconductor layers and said at least one third semiconductor layer;
• and
• a second cell including a plurality of second semiconductor layers of the second conductivity type selectively formed in the surface area of the first semiconductor layer of the first conductivity type and a fifth semiconductor layer of the second conductivity type provided between adjacent second semiconductor layers of the second conductivity type and having impurity concentration that is lower than that of the plurality of second semiconductor layers,
• wherein the first semiconductor layer includes a low-resistance layer of the first conductivity type having impurity concentration that is higher than that of the first semiconductor layer;
• and
• the first cell further includes a seventh semiconductor layer of the first conductivity type provided between adjacent second semiconductor layers and having impurity concentration that is lower than that of the low-resistance layer.

An insulated gate semiconductor device comprising:

• a first semiconductor layer of a first conductivity type;
• a low-resistance layer of the first conductivity type provided in the first semiconductor layer and having impurity concentration that is higher than that of the first semiconductor layer;
• a plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the low-resistance layer;
• at least one third semiconductor layer of the first conductivity type formed in a surface area of each of the plurality of second semiconductor layers;
• a plurality of first main electrodes connected to the plurality of second semiconductor layers and said at least one third semiconductor layer, respectively;
• a fourth semiconductor layer formed on a bottom of the first semiconductor layer;
• a second main electrode connected to the fourth semiconductor layer;
• a control electrode formed on a surface of each of the plurality of second semiconductor layers, said at least one third semiconductor layer, and the low-resistance layer with a gate insulation film interposed therebetween;
• and
• a plurality of fifth semiconductor layers of the second conductivity type provided in the low-resistance layer, connected to adjacent second semiconductor layers, and having impurity concentration that is lower than that of the plurality of second semiconductor layers,
• wherein a seventh semiconductor layer of the first conductivity type having impurity concentration that is lower than that of the low-resistance layer is provided between the plurality of fifth semiconductor layers.

An insulated gate semiconductor device comprising:

• a first semiconductor layer of a first conductivity type;
• a low-resistance layer of the first conductivity type provided in the first semiconductor layer and having impurity concentration that is higher than that of the first semiconductor layer;
• a plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the low-resistance layer;
• at least one third semiconductor layer of the first conductivity type formed in a surface area of each of the plurality of second semiconductor layers;
• a plurality of first main electrodes connected to the plurality of second semiconductor layers and said at least one third semiconductor layer, respectively;
• a fourth semiconductor layer formed on a bottom of the first semiconductor layer;
• a second main electrode connected to the fourth semiconductor layer;
• a control electrode formed on a surface of each of the plurality of second semiconductor layers, said at least one third semiconductor layer, and the low-resistance layer with a gate insulation film interposed therebetween;
• and
• a plurality of fifth semiconductor layers of the second conductivity type provided in the low-resistance layer, connected to adjacent second semiconductor layers, and having impurity concentration that is lower than that of the plurality of second semiconductor layers.