Clock control circuit and method

A clock control circuit comprising:

• an input buffer receiving a clock signal input thereto;
• a multiphase clock generating circuit, receiving an output signal of said input buffer, for generating and outputting a plurality of clocks, phases of which differ from one another;
• a selector circuit, receiving a plurality of clocks output from said multiphase clock generating circuit, for selecting and outputting one of the received clocks;
• a first variable delay circuit for delaying an output signal of said selector circuit;
• a first clock buffer receiving an output signal of said first variable delay circuit;
• a phase comparator circuit for detecting and outputting a phase difference between one of the clocks output from said multiphase clock generating circuit and an output signal of said first clock buffer;
• a filter for smoothing a phase-difference detection signal output from said phase comparator circuit,
• a delay time of said first variable delay circuit varied by the output signal of said filter;
• a second variable delay circuit receiving the output signal of said input buffer and delaying said signal received, a delay time of said second variable delay circuit varied by the output signal of said filter, and
• a second clock buffer receiving the output signal of said second variable delay circuit for outputting an output clock signal.

A clock control circuit comprising:

• an input buffer for receiving a clock signal input thereto;
• a multiphase clock generating circuit, receiving an output signal of said input buffer as an input for generating and outputting a plurality of clocks, phases of which differ from one another;
• a selector circuit, receiving a plurality of clocks output from said multiphase clock generating circuit as inputs, for selecting and outputting one of the received clocks;
• a first variable delay circuit for delaying an output signal of said selector circuit;
• a first clock buffer receiving an output signal of said first variable delay circuit;
• a phase comparator circuit for detecting and outputting a phase difference between one of the clocks output from said multiphase clock generating circuit and an output signal of said first clock buffer;
• and
• a filter for smoothing the phase-difference detection signal output from said phase comparator circuit;
• a delay time of said first variable delay circuit being varied by the output of said filter;
• a second variable delay circuit, receiving the output signal of said input buffer, a delay time of said second variable delay circuit varied by the output signal of said filter;
• an adder circuit for adding the output signal of said filter and a set value entered to said adder circuit;
• a third variable delay circuit receiving the output signal of said first input buffer, a delay time of said third variable delay circuit varied by the output signal of said adder circuit;
• and
• second and third clock buffers, receiving output signals of said second and third variable delay circuits, respectively, for producing respective ones of output clock signals.

A clock control circuit comprising:

• a phase-difference generating circuit for outputting a signal obtained by delaying an input clock signal by a predetermined phase difference on the basis of phase decision information applied thereto;
• a first variable delay circuit for delaying an output signal of said phase-difference generating circuit;
• a phase comparator circuit for detecting and outputting a phase difference between an output signal of said phase-difference generating circuit and an output signal output from said first variable delay circuit;
• a filter for smoothing a phase-difference detection signal output from said phase comparator circuit;
• a delay time of said first variable delay circuit varied by the output of said filter;
• and
• a second variable delay circuit, a delay time of which is varied by the output of said filter;
• wherein a signal obtained by delaying the input clock by said second variable delay circuit is delivered as an output clock signal.

A clock control circuit comprising:

• an input buffer for receiving a clock input thereto;
• a phase-difference generating circuit, receiving an output signal of said input buffer and phase decision information, for outputting a signal obtained by delaying the output signal of said input buffer by a predetermined phase difference on the basis of the phase decision information;
• a first variable delay circuit for delaying an output signal of said phase-difference generating circuit;
• a first clock buffer receiving an output signal of said first variable delay circuit as an input for driving a dummy load;
• a phase comparator circuit for detecting and outputting a phase difference between an output signal of said phase-difference generating circuit and an output signal of said first clock buffer;
• a filter for smoothing a phase-difference detection signal output from said phase comparator circuit,
• a delay time of said first variable delay circuit varied by the output of said filter;
• a second variable delay circuit, receiving an output signal of said input buffer, a delay time of second variable delay circuit varied by the output of said filter;
• and
• a second clock buffer, receiving an output signal of said second variable delay circuit as an input for outputting an output clock signal.

A clock control circuit comprising:

• an input buffer for receiving a clock input thereto;
• a phase-difference generating circuit, receiving an output signal of said input buffer and phase decision information applied thereto as inputs, for outputting a signal obtained by delaying the output signal of said input buffer by a predetermined phase difference on the basis of the phase decision information;
• a first variable delay circuit for delaying an output signal of said phase-difference generating circuit;
• a first clock buffer receiving an output signal of said first variable delay circuit as an input for driving a dummy load;
• a phase comparator circuit for detecting and outputting a phase difference between an output signal of said phase-difference generating circuit and an output signal of said first clock buffer;
• a filter for smoothing a phase-difference detection signal output from said phase comparator circuit,
• a delay time of said first variable delay circuit varied by an output signal of said filter;
• a second variable delay circuit, receiving the output signal of said input buffer as an input, a delay time of second variable delay circuit varied by the output signal of said filter;
• an adder circuit for adding the output signal of said filter and an entered set value;
• a third variable delay circuit, receiving the output signal of said input buffer as an input, a delay time of the third variable delay circuit varied by the output of said adder circuit;
• and
• second and third clock buffers, receiving output signals of said second and third variable delay circuits, respectively, for outputting first and second output clock signals.

A clock control circuit comprising:

• an input buffer for receiving a clock input thereto;
• a phase-difference generating circuit, receiving an output signal of said input buffer from one input terminal and one output clock from another input terminal, for producing two output signals, having a phase difference decided by phase decision information input thereto as a control signal, from the output of said input buffer and the output clock;
• a phase comparator circuit for detecting and outputting a phase difference between the two outputs of said phase-difference generating circuit;
• a filter for smoothing a phase-difference detection signal output from said phase comparator circuit;
• a first variable delay circuit for delaying the output signal of said input buffer;
• and
• a first clock buffer, receiving an output signal of said first variable delay circuit an input, for producing an output clock;
• wherein the output clock of said first clock buffer is supplied as said output clock applied to said another input terminal of said phase-difference generating circuit;
• and
• wherein a delay time of said first variable delay circuit is varied by the output signal of said filter.

A clock control circuit comprising:

• a phase-difference generating circuit, receiving an input clock signal and an output clock signal, for producing first and second output signals, a phase difference between the first and second output signals decided by phase decision information entered thereto, based upon the input clock signal and the output clock signal;
• a first variable delay circuit for delaying the second output signal of said phase-difference generating circuit;
• a phase comparator circuit for detecting and outputting a phase difference between the first and second output signals output from said phase-difference generating circuit;
• a filter for smoothing a phase-difference detection signal output from said phase comparator circuit,
• a delay time of said first variable delay circuit varied by the output signal of said filter;
• and
• a second variable delay circuit having a delay time varied by the output signal of said filter;
• wherein signals obtained by delaying the input clock by each of said first and second variable delay circuits are delivered as first and second output clock signals, and the first output clock signal enters said phase-difference generating circuit as the output clock signal.

A clock control circuit comprising:

• an input buffer for receiving a clock signal input thereto;
• a phase-difference generating circuit, receiving an input clock signal output from said input buffer from one input terminal and one output clock signal from another input terminal, for producing first and second output signals having a phase difference decided by phase decision information entered thereto, said first and second output signals being signals obtained by delaying the input clock signal and the output clock signal by an interior-division ratio decided by the phase decision information;
• a phase comparator circuit for detecting and outputting a phase difference between the first and second signals output from said phase-difference generating circuit;
• a filter for smoothing a phase-difference detection signal output from said phase comparator circuit;
• a first variable delay circuit, having a delay time varied based upon the output signal of said filter, for delaying the output signal of said input buffer;
• a first clock buffer, receiving an output signal of said first variable delay circuit, for producing a first output clock signal, the first output clock being fed to said phase-difference generating circuit as said one output clock;
• an adder circuit for adding the output signal of said filter and an entered set value;
• a second variable delay circuit, receiving the output signal of said input buffer, and having a delay time varied by the output signal of said adder circuit;
• and
• a second clock buffer, receiving an output signal of said second variable delay circuit, for producing a second output clock signal.

A clock control method comprising the steps of:

• generating, by a multiphase clock generating circuit receiving an input clock signal from an input buffer, a plurality of clocks, the phases of which differ from one another, from the input clock signal;
• selecting one of the clocks from said multiphase clock generating circuit by a selector circuit;
• delaying the selected clock by a first variable delay circuit;
• detecting, by a phase comparator circuit, a phase difference between an output signal of a clock buffer receiving an output signal from said first variable delay circuit and one of the clocks output from said multiphase clock generating circuit, and variably adjusting a delay time of said first variable delay circuit on the basis of a signal obtained by smoothing the result of the phase comparison by a filter;
• and
• producing an output clock signal, having a desired phase relationship with respect to the input clock signal, from a clock buffer that receives an output signal from a second variable delay circuit, to which an output signal of said input buffer is fed and which has a delay time varied by the output signal of said filter.

A clock control method comprising the steps of:

• supplying an output signal of an input buffer, which receives an entered clock, to a phase-difference generating circuit;
• generating, by said phase-difference generating circuit, a signal obtained by delaying an output signal of said input buffer by a predetermined phase difference on the basis of phase decision information applied thereto;
• detecting, by a phase comparator circuit, a phase difference between an output of a clock buffer dummy, which receives as an input an output signal from a first variable delay circuit that delays an output signal of said phase-difference generating circuit, and the output signal of said phase-difference generating circuit;
• smoothing a result of the phase comparison by a filter and varying delay time of said first variable delay circuit by an output signal from said filter;
• and
• producing an output clock signal from a clock buffer which receives as an input an output signal from a second variable delay circuit which receives an output signal of said input buffer and which has its delay time varied by the output of said input buffer.

A clock control method comprising the steps of:

• supplying an output signal of an input buffer, which receives an entered clock, to a phase-difference generating circuit from one input terminal thereof, and supplying one output signal to said phase-difference generating circuit from another input terminal thereof;
• outputting, from said phase-difference generating circuit, two signals having a desired phase difference on the basis of entered phase decision information, the two signals being produced from an output signal of said input buffer and said output signal;
• detecting, by a phase comparator circuit, a phase difference between the two signals output from said phase-difference generating circuit;
• smoothing a result of the phase comparison by a filter;
• producing an output signal from a first clock buffer that receives an output from a first variable delay circuit that delays an output signal from said input buffer;
• supplying the output signal of said first clock buffer to the other input terminal of said phase-difference generating circuit;
• and
• varying delay time of said first variable delay circuit by an output from said filter.