Semiconductor integrated circuit and its design methodology
AssigneeHitachi, Ltd.
InventorIchiro Kohno
Life of this patent
Estimating the term…
Abstract
A method and device are provided for applying logic BIST at speed for large-scale and high-performance logic circuits without increasing test time, and decreasing test costs as a result. In one example, a logic BIST controller is divided into two portions. A clock signal having a small delay is used-to drive a partial circuit that supplies a user circuit with a scan enable signal and a clock signal. A clock signal having a large delay is used to drive a partial circuit that supplies the user circuit with a test pattern and collects a test result.
Claims10
A semiconductor integrated circuit comprising:
- a logic circuit including having one or more flip-flops and one or more combinational circuits;
- and
- a test control circuit including,
- a control circuit configured to output a control signal for controlling connection states of the one or more flip-flops, and
- a pattern generation circuit configured to generate a test pattern for the logic circuit, wherein when the control signal is in a first state, each of the one or more flip-flops is connected to other flip-flops without passing through the one or more combinational circuits and transmits a test pattern generated from the pattern generation circuit to the other flip-flops, and wherein when the control signal is in a second state, each of the one or more flip-flops is connected to any of the one or more combinational circuits and outputs a stored test pattern to a connected combinational circuit, and wherein a phase of a clock signal to drive the control circuit advances further than a phase of a clock signal to drive the pattern generation circuit.
A method of designing a semiconductor integrated circuit including a logic circuit having one or more flip-flops, one or more combinational circuits, and a test control circuit having a control circuit to output a control signal for controlling connection states of the flip-flops and a pattern generation circuit to generate a test pattern for the logic circuit, the method comprising:
- arranging the-logic circuit and the test control circuit;
- performing a clock tree synthesis for the logic circuit and the test control circuit;
- calculating a first delay of a first clock signal supplied to the flip-flops of the logic circuit and a second delay of a second clock signal supplied to the pattern generation circuit of the test control circuit;
- and
- performing another clock tree synthesis.
Dependencies are inferred from the claim text.