System and method for temporally isolating environmentally sensitive integrated circuit faults

A method for temporally isolating a fault within an integrated circuit comprising the steps of:

• determining a marginally failing environmental condition associated with the fault;
• identifying a clock cycle Tmax at which the fault was first detected;
• determining a candidate clock cycle at which the fault may have occurred;
• iteratively performing the substeps of:
• applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition;
• and
• adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application;
• and
• determining an exact clock cycle at which the fault occurred in a maximum of Log2 (Tmax+1) substep iterations.

A method for temporally isolating a fault within an integrated circuit comprising the steps of:

• determining a marginally failing environmental condition associated with the fault;
• determining an upper bound clock cycle corresponding to a latest clock cycle at which the fault may have occurred;
• determining a lower bound clock cycle corresponding to an earliest clock cycle at which the fault may have occurred;
• determining a candidate clock cycle at which the fault may have occurred;
• applying a test pattern subset from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition;
• and
• adjusting the candidate clock cycle and one from the group of the upper bound clock cycle and the lower bound clock cycle based upon whether the fault occurred during test pattern subset application.