Universal serial bus circuit and data structure
AssigneeOki Electric Industry Co., Ltd.
InventorEiji Komoto
Life of this patent
Estimating the term…
Abstract
A USB circuit that can prevent phase difference between a signal pair with high precision without the need for strict design conditions. In a preferred embodiment of this USB circuit, the USB controller thereof comprises a flip-flop pair to match the timings of a signal pair output to an output signal line pair and a flip-flop pair to match the timings of a signal pair input from an input signal line pair, and the USB driver thereof comprises a third flip-flop pair to match the timings of a signal pair input from the output signal line pair, and a fourth flip-flop pair to match the timings of a signal pair output to the input signal line pair.
Claims17
A universal serial bus circuit comprising:
- a universal serial bus controller formed on a semiconductor chip;
- a universal serial bus driver formed on said semiconductor chip;
- an output signal line pair and an input signal line pair formed on said semiconductor chip for connecting said universal serial bus controller and said universal serial bus driver;
- a first flip-flop pair provided in said universal serial bus controller for matching the timing of the signal pair output to said output signal line pair;
- a second flip-flop pair provided in the universal serial bus controller for matching the timing of the signal pair input from said input signal line pair;
- a third flip-flop pair provided in the universal serial bus driver for matching the timing of said signal pair input from said output signal line pair;
- and
- a fourth flip-flop pair provided in the universal serial bus driver for matching the timing of said signals output to said input signal line pair.
A universal serial bus circuit comprising:
- a universal serial bus controller formed on a semiconductor chip;
- a universal serial bus driver formed on said semiconductor chip;
- an output signal line pair and an input signal line pair formed on said semiconductor chip for connecting said universal serial bus controller and said universal serial bus driver;
- a first flip-flop pair provided in said universal serial bus controller for matching the timing of the signal pair output to said output signal line pair;
- a second flip-flop pair provided in said universal serial bus controller for matching the timing of the signal pair input from said input signal line pair;
- a first delay adjustment circuit that adjusts the signal propagation delay time for at least one of said output signal line pair in accordance with the value of a delay control signal;
- and
- a second delay adjustment circuit that adjusts the signal propagation delay time for at least one of said input signal line pair in accordance with the value of a delay control signal.
A data structure indicating a information in accordance with one or more pre-designed circuit blocks, wherein
- said information is used in an apparatus which designs a semiconductor integrated circuit by performing layout and wiring of the pre-designed circuit blocks:
- and
- a universal serial bus driver is constructed by one block which contains a first flip-flop pair to match the timings of the signal pair input from the output signal line pair, a second flip-flop pair to match the timings of the signal pair output to the input signal line pair, a first driver pair that output to the outside the signal pair output from said first flip-flop pair, and a second driver pair that output to said second flip-flop pair the signal pair input from the outside.
Dependencies are inferred from the claim text.